We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW fieldeffect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.Over the past several years, semiconductor NWs 1,2 and carbon nanotubes 3 have been actively explored as the potential materials for future electronic components. These chemically derived single-crystalline nanostructures present unique advantages over conventional semiconductors, as they enable integration of high-performance device elements onto virtually any substrate 4-6 with scaled on-currents and switching speeds higher than state-of-the-art planar Si structures. 7,8 These unique electrical properties and the intrinsically miniaturized dimensions of NW and carbon nanotube building blocks may facilitate the continuation of Moore's law and the evolutionary quest for ever faster and smaller electronics well into the future. More uniquely, the capability of assembling high-performance NW building blocks with diverse functional properties could enable novel circuit concepts such as 3D integrated electronics, 9 where 3D structure arises from sequential assembly 10-12 of NWs into vertically stacked device layers.Indeed, there has been considerable interest in multilayer electronics, as they offer a more efficient interconnection and processing of digital information. [13][14][15] However, materials-and fabrication-related challenges have presented major obstacles in achieving truly 3D integrated circuits based on the conventional Si CMOS technology, and the need for a new technology remains critical. Here, we report the monolithic integration of individual and parallel arrays of crystalline NWs as multifunctional and multilayer circuits...

Transparent electrodes that can remain electrically conductive and stable under large mechanical deformations are highly desirable for applications in flexible and wearable electronics. This paper describes a comprehensive study of the electrical, optical, and mechanical properties of hybrid nanostructures based on two-dimensional graphene and networks of one-dimensional metal nanowires, and their use as transparent and stretchable electrodes. Low sheet resistance (33 Ω/sq) with high transmittance (94% in visible range), robust stability against electric breakdown and oxidation, and superb flexibility (27% in bending strain) and stretchability (100% in tensile strain) are observed, and these multiple functionalities of the hybrid structures suggest a future promise for next generation electronics. The use of hybrid electrodes to fabricate oxide semiconductor transistors and single-pixel displays integrated on wearable soft contact lenses with in vivo tests are demonstrated.

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Radial core/shell nanowires (NWs) represent an important class of one-dimensional (1D) systems with substantial potential for exploring fundamental materials electronic and photonic properties. Here, we report the rational design and synthesis of InAs/InP core/shell NW heterostructures with quantum-confined, high-mobility electron carriers. Transmission electron microscopy studies revealed single-crystal InAs cores with epitaxial InP shells 2−3 nm in thickness, and energy-dispersive X-ray spectroscopy analysis further confirmed the composition of the designed heterostructure. Room-temperature electrical measurements on InAs/InP NW field-effect transistors (NWFETs) showed significant improvement in the on-current and transconductance compared to InAs NWFETs fabricated in parallel, with a room-temperature electron mobility, 11 500 cm 2 /Vs, substantially higher than other synthesized 1D nanostructures. In addition, NWFET devices configured with integral high dielectric constant gate oxide and top-gate structure yielded scaled on-currents up to 3.2 mA/µm, which are larger than values reported for other n-channel FETs. The design and realization of high electron mobility InAs/InP NWs extends our toolbox of nanoscale building blocks and opens up opportunities for fundamental and applied studies of quantum coherent transport and high-speed, low-power nanoelectronic circuits.Central to the "bottom-up" vision for nanoscale science and technology is the design and rational synthesis of building blocks with well-defined physical properties. 1 Semiconductor NWs represent a broad class of one-dimensional (1D) building blocks in which significant progress is being made in atomic to nanometer scale control of materials morphology, size, and composition, 1-4 including the growth of axial, 2 radial, 3 and branched 4 NW heterostructures. In the case of radial NW heterostructures, 3,5a-c the controlled growth of one or more shells can passivate existing surface states, enable new interface properties, and introduce unique electronic and photonic function. For example, the energy band line-up at the Ge and Si interface of Ge/Si core/shell NWs 5 leads to the accumulation of high-mobility hole carriers, which have enabled fundamental studies of quantum transport 5a,b and the realization of the highest performance p-channel NWFETs to date. 5c There has also been considerable effort placed on developing high electron mobility NWs with InAs, which has a small electron effective mass and correspondingly high bulk electron mobility, 6 the focus of a number of groups. 7 Reported electron mobilities for InAs NWs have been substantially lower than bulk values 7 and thus suggest that scattering processes in the NWs, including ionized impurity and surface scattering, 7d reduce mobility. Hence, structures that passivate and/or protect the surface of InAs NWs might lead to enhanced transport properties. To this end, we report studies of InAs/InP core/shell NWs in which the InAs surfaces have been passivated with a nanometer-thick ep...

Field-effect transistor (FET)-based biosensors allow label-free detection of biomolecules by measuring their intrinsic charges. The detection limit of these sensors is determined by the Debye screening of the charges from counter ions in solutions. Here, we use FETs with a deformed monolayer graphene channel for the detection of nucleic acids. These devices with even millimeter scale channels show an ultra-high sensitivity detection in buffer and human serum sample down to 600 zM and 20 aM, respectively, which are ∼18 and ∼600 nucleic acid molecules. Computational simulations reveal that the nanoscale deformations can form 'electrical hot spots' in the sensing channel which reduce the charge screening at the concave regions. Moreover, the deformed graphene could exhibit a band-gap, allowing an exponential change in the source-drain current from small numbers of charges. Collectively, these phenomena allow for ultrasensitive electronic biomolecular detection in millimeter scale structures.