Programmable nanowire circuits for nanoprocessors

Abstract

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Programmable Resistive-Switch Nanowire Transistor Logic Circuits

“…Compared to charge-based programming of active/inactive nodes, 19,20 which has analogies to flash memory, 24 resistive switch elements provide potential advantages in terms of nonvolatility or retention, scaling, and programming speed and endurance. 21−23 First, in the resistive switch the state change is largely due to a local structural/ composition change in the material between switch electrodes, and the retention is often projected to be beyond years.…”

“…25 Specifically, the effective voltage on RG will be reduced from V CG in the low-R state (upper panel) to [C 1 /(C 1 + C 2 )]V CG in the high-R state (bottom panel) (see below for quantitative analysis and comparison with device experiments). The different thresholds associated with the two resistive switch states yield a hysteresis loop for transistor drain current versus V CG (Figure 1c) such that we can define a programmable logic window (gray region, Figure 1c), 1,19,20 where the resistive-switch nanowire transistor can serve as a typical transistor (red curve, "active") or as a passive resistor (blue curve, "inactive").…”

“…Each crossbar array functions as a NOR logic gate unit, and in combination can yield complete logic functions dependent only on programming and the ultimate array sizes. 3,19,20 For our demonstration, we have considered a 2-to-4 demultiplexer with active resistive switch nodes indicated by green dots; an equivalent circuit is also shown for comparison (inset, Figure 4a We fabricated the 2-to-4 demultiplexer resistive-switch nanowire transistor crossbar circuit by assembling aligned Ge/Si nanowires using nanocombing 20,39 followed by conventional lithography. 34 Figure 4b (left panel) shows a SEM image of one of the fabricated arrays consisting of 10 nanowires with 6 device nodes on each nanowire.…”

“…This level of robustness is substantially greater than the retention of hours in charge-based systems. 14,19,20 In addition, the stacked resistive switch elements (nodes in crossbar) are attractive for minimizing the area per node compared with charge-based nanowire programmable device elements. 19,20 Specifically, this study demonstrates that programming capability is maintained for a gate length of 50 nm with a 30 nm width switch element, as opposed to a >200 nm feature demonstrated in charge-based nanowire crossbar structures.…”

“…14,19,20 In addition, the stacked resistive switch elements (nodes in crossbar) are attractive for minimizing the area per node compared with charge-based nanowire programmable device elements. 19,20 Specifically, this study demonstrates that programming capability is maintained for a gate length of 50 nm with a 30 nm width switch element, as opposed to a >200 nm feature demonstrated in charge-based nanowire crossbar structures. 19,20 The resistive switch element does have a disadvantage compared to charge-based switches because of the additional independent RG gates required for each node.…”