In most digital applications like audio, speech, graphics and video, people can easily gather valuable data from output having small errors. Thus, it is not important to give exactly correct output. Thinking about the benefit of unwinding in precision, several approximate adders made from different techniques are proposed in this paper for error resilient applications. Approximate adder has been designed to decrease circuit complexity at transistor level. By decreasing the transistor count connected in series, energy consumption can be decreased. The propagation delay in the circuit is significantly reduced due to low power. Simulation results for proposed adders indicate that in contrast to the traditional adder for the random inputs, the adder suggested can achieve reduction of up to 40% power-delay product. The proposed adder minimizes the circuit area (number of transistors) substantially relative to current designs. All circuits are simulated with the gpdk 90-nm technology in Cadence Virtuoso.
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