This paper considers problems related to hardware implementation of computational process with conditional jumps. Hardware refers to asynchronous pipeline organization at microoperational level. Exploration is dedicated to one of the tasks presented in (Tyanev, 2009) concerning to micropipeline controller design to control micropipeline stage into joint dot of branch algorithm. Joint dot is the point at which few preceding branches are combined. It appears inevitably into conditional jump structures and this is the reason for the actuality of its problem. Analysis of this new task is presented and request arbitration functioning principles are formulated for the incoming to joint dot requests. The arbiter is responsible for the fair choice on which depends steady peformance of separate pipeline brances. Paper also describes pipeline controller synthesis and analysis of its operation in two variants: about 2phase and 4-phase data transfer protocol. The synthesized asynchronous arbiter scheme is invariant to the type of pipeline protocol.
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