The paper focuses on the problem of hardware implementation of the computational process containing conditional transitions. Asynchronous organization of pipelines at microoperational level is provided for the hardware. Its characteristic feature is that it includes both one and multi-cycle micropipeline units. Because of these circumstances, the outgoing pipeline results do not correspond in the same order to the tasks running in the pipeline. The article presents the synthesized original logical structure of the micropipeline buffer and a specific to its service strategy through which their correct order is restored when reading results from the buffer. Another programming model of the structure of the buffer is described, by which its behavior was studied in different possible situations. In addition, a programming model of the structure of the buffer was created and its behavior in different possible situations is examined. The results of numerical experiments with the programming model are presented. Based on them recommendations are formulated about the parameters of the buffer and the structure of the pipeline.
This paper considers problems related to hardware implementation of computational process with conditional jumps. Hardware refers to asynchronous pipeline organization at microoperational level. Exploration is dedicated to one of the tasks presented in (Tyanev, 2009) concerning to micropipeline controller design to control micropipeline stage into joint dot of branch algorithm. Joint dot is the point at which few preceding branches are combined. It appears inevitably into conditional jump structures and this is the reason for the actuality of its problem. Analysis of this new task is presented and request arbitration functioning principles are formulated for the incoming to joint dot requests. The arbiter is responsible for the fair choice on which depends steady peformance of separate pipeline brances. Paper also describes pipeline controller synthesis and analysis of its operation in two variants: about 2phase and 4-phase data transfer protocol. The synthesized asynchronous arbiter scheme is invariant to the type of pipeline protocol.
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