Static instruction schedulinyis un important optimization to exploit instruction. level parallelisni. If the scheduler has to consider resource construints l o prevent structural huzards, 7lSIlCldhJ the processor tirniny i s simulated by overlayiny binury mutrices representing the resource usuye of instructions. This technique as ruther time consuming. I n this urticle it is shoiiin thet the timiny cun be simulated b y u deterministic finite uutomaton und the matrix operations f o r u simulation step are repluced by two tuble lookups. A prototype implementation shows thut ubout a eiyhtcenfold speedup of the simulution can be expfated. This perfofrmunce gain can be used either to speed up ezistiny scheduliny alyorithms or t o use more c o m p l e z a1goritlrnr.s to improue scheduling results.