Instruction scheduling for the Motorola 88110

Smotherman, Mark; Chawla, Shuchi; Cox, Stan; Malloy, Brian A.

doi:10.1109/micro.1993.282761

Cited by 10 publications

References 6 publications

(1 reference statement)

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Iterative Modulo Scheduling

Rau

1996

Int J Parallel Prog

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modulo scheduling, instruction scheduling, software pipelining, loop scheduling Modulo scheduling is a framework within which algorithms for the software pipelining of innermost loops may be defined. The framework specifies a set of constraints that must be met in order to achieve a legal modulo schedule. A wide variety of algorithms and heuristics can be defined within this framework. Little work has been done to evaluate and compare alternative algorithms and heuristics for modulo scheduling from the viewpoints of schedule quality as well as computational complexity. This, along with a vague and unfounded perception that modulo scheduling is computationally expensive as well as difficult to implement, have inhibited its incorporation into product compilers. This report presents iterative modulo scheduling, a practical algorithm that is capable of dealing with realistic machine models. The report also characterizes the algorithm in terms of the quality of the generated schedules as well the computational expense incurred.

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Iterative Modulo Scheduling

Rau

1996

Int J Parallel Prog

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A theory for software-hardware co-scheduling for ASIPs and embedded processors

Govindarajan

Altman²,

Gao

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors

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Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded processors. Existing techniques deal with either scheduling hardware pipelines to obtain higher throughput or software pipeline -an instruction scheduling technique for iterative computation -loops for exploiting greater ILP. We integrate these techniques to co-schedule hardware and software pipelines to achieve greater instruction throughput.In this paper, we develop the underlying theory of co-scheduling, called the ModuloScheduled Pipeline (or MS-Pipeline) theory. More specifically, we establish the necessary and sufficient condition for achieving the maximum throughput in a given pipeline operating under modulo scheduling. Further, we establish a sufficient condition to achieve a specified throughput, based on which we also develop a methodology for designing the hardware pipelines that achieve such a throughput.

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An enhanced Co-scheduling method using reduced MS-state diagrams

Govindarajan

Rao

Altman³

et al.

Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processin

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Instruction scheduling methods based on the construction of state diagrams (or automata) have been used for architectures involving deeply pipelined function units. However, the size of the state diagram is prohibitively large, resulting in high execution time and space requirement. In this paper, we present a simple method for reducing the size of the state diagram by recognizing unique paths of a state diagram. Our experiments show that the number of paths in the reduced state diagram is significantly lowerby 1 to 3 orders of magnitude-compared to the number of paths in the original state diagram. Using the reduced MS-state diagrams, we develop an efficient software pipelining method. The proposed software pipelining algorithm produced efficient schedules and performed better than Huff's Slack Scheduling method, and the original Co-scheduling method, in terms of both the initiation interval (II) and the time taken to construct the schedule.

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Instruction scheduling for the Motorola 88110

Cited by 10 publications

References 6 publications

Iterative Modulo Scheduling

Iterative Modulo Scheduling

A theory for software-hardware co-scheduling for ASIPs and embedded processors

An enhanced Co-scheduling method using reduced MS-state diagrams

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