The solar power generation system is being increasingly connected to the low power distribution system due to its low cost and abundant availability. The interconnection of the solar power generation system demands new and efficient power converters to provide sufficient boost factor for the solar panel output voltage. This paper presents a Modified Coupled Inductor, Capacitor Multiplier (MCICM) direct current (DC)–DC boost converter to provide high boost factor for the solar panel output voltage and to maximize the benefits of the grid‐interfacing three‐phase three‐wire inverter. The fuzzy logic‐based DC‐link voltage controller and hysteresis current controller (HCC) are also proposed to enhance the power transfer ability of the small power grid‐connected inverter. The new topology of boost converter constructed with the coupled inductors, capacitor, and high‐frequency transformers is demonstrated through the series of tests carried out with extensive MATLAB/Simulink simulation studies. The SPARTAN 3 field‐programmable gate array (FPGA)‐based prototyping model validated the performance of the proposed topology, experimentally.
This research article presents a modified novel crisscross augmented ladder (CCAL) structured multilevel inverter (MLI). MLIs can be operated in symmetric and asymmetric binary and ternary voltage ratios. The modified structure comprises a generalized unit (CCAL) and an extendable structure; this structure can be extended to generate more stair case waveform. The foremost benefit of this modified structure is to curb the conduction path of active switches. The utilized structure uses only four active conduction paths in all modes. However, an MLI has complexity, such as a higher number of switches and bulky controlling driver circuits which need superior controls. This article suggests a prominent solution for the above issues. The subtle CCAL is a governed multicarrier pulse width modulation scheme with the savvy fuzzy logic controller and, therefore, added benefits, such as lower switch stress, lower switching loss, and lower dv/dt stress. Hitherto, many topologies are emerging to curb the component count reduction structure; among them it is an attempt to curtail the active conduction path. The working capability of the presented system is substantiated with a simulation study carried out in MATLAB R2017a and viability hardware (Xilinx FPGA) proof of concept to validate the effectiveness.
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