Current collapse due to the trapping/de-trapping of the carriers at the surface and in the bulk of a 0.25 μm gate length AlGaN/GaN high electron mobility transistor (HEMT) is investigated using 2D Technology Computer Aided Design (TCAD) transient simulations. Gate and drain pulse techniques are used to study the dynamic picture of trapping and de-trapping of carriers within drift-diffusion and hydrodynamic transport models. In addition, coupled electrical and thermal simulations are performed to model the energy exchange of the carriers with the lattice and to predict electron temperature in the channel. It is found that current degradation upon electrical stress is due to two different types of traps, donor-like traps and acceptor-like traps, respectively. The collapse next to 5% and 75% was observed for bulk and surface traps, respectively. The combined effect of surface and bulk traps on current transient characteristics has been investigated and simulations are in a very good qualitative agreement with the experimental observations.
This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices' pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gatelag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computeraided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level.
A novel enhancement mode structure, a buried gate gallium nitride (GaN) high electron mobility transistor (HEMT) with a breakdown voltage (BV) of 1400 V-4000 V for a source-to-drain spacing (L SD ) of 6 μm-32 μm, is investigated using simulations by Silvaco Atlas. The simulations are based on meticulous calibration of a conventional lateral 1 μm gate length GaN HEMT with a source-to-drain spacing of 6 μm against its experimental transfer characteristics and BV. The specific on-resistance R S for the new power transistor with the source-to-drain spacing of 6 μm showing BV = 1400 V and the source-to-drain spacing of 8 μm showing BV = 1800 V is found to be 2.3 mΩ • cm 2 and 3.5 mΩ • cm 2 , respectively. Further improvement up to BV = 4000 V can be achieved by increasing the source-to-drain spacing to 32 μm with the specific on-resistance of R S = 35.5 mΩ • cm 2 . The leakage current in the proposed devices stays in the range of ∼5 × 10 −9 mA mm −1 .
This letter presents first-ever fabricated GaN split-current magnetic sensor device. Device operation and key manufacturing steps are also presented. The measured relative current sensitivity is constant at 14 % T-1 for wide mT range of the magnetic field. Constant sensitivity of a fabricated sensor can be attributed to device's 2DEG nature, i.e. its high electron concentration and mobility, and very small layer thickness.
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