Virtual platform (ViP), or ESL (Electronic System Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard disk system called Hybrid-HDD that is one of the main features in the Windows VISTA (R). First, we summarize how we developed the ViP including the levels of timing accuracy of models, automatic generation of models from RTL code, external subsystem models, etc. Then, we explain how we exploited the ViP in software optimization. Compared with the conventional flow of software development, e.g. based on the real board, the ViP gives a better profiling capability thereby allowing designers to find more chances of code optimization. Based on the simulation and analysis with the ViP, the software optimization could improve system performance by more than 50%. However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.
3D stacked memory enables more off-chip DDR memories. Redesigning existing IPs to exploit the increased memory parallelism will be prohibitively costly. In our work, we propose a practical approach to exploit the increased bandwidth and reduced latency of multiple off-chip DDR memories while reusing existing IPs without modification. The proposed approach is based on two new concepts: transaction id renaming and distributed soft arbitration. We present two on-chip network components, request parallelizer and read data serializer, to realize the concepts. Experiments with synthetic test cases and an industrial strength DTV SoC design show that the proposed approach gives significant improvements in total execution cycle (21.6%) and average memory access latency (31.6%) in the DTV case with a small area overhead (30.1% in the on-chip network, and less than 1.4% in the entire chip).
IntroductionDynamic voltage scaling (DVS) is one of the most effective methods in reducing both switching and leakage power consumption. There have been two classes of DVS methods: intertask and intra-task DVS. Inter-task DVS methods [1][2] determines the performance level at a task granularity while intra-task DVS methods at finer granularitiesIn intra-task DVS, workload estimation plays a central role since the performance level (normalized w.r.t. maximum frequency) in the middle of task execution is dynamically determined, mostly, by X/T, where X is the estimated remaining workload and T is the time to deadline. Thus, the accuracy of workload estimation determines the quality of intra-task DVS method.Several methods of workload estimation have been proposed: worst case execution time [3][4], average case execution path [5], average energy execution path [6], and statistical methods [7]. Among them, the statistical method and average energy execution path-based one are reported to give the best reduction in average switching energy consumption since they provide global minimum solutions based on mathematical formulations. However, the leakage power consumption is not minimized by the methods since they minimize only the switching energy based on the assumption of P ~ f 3 (P ~ CV 2 f ~ f 3 since V ~ f ). Leakage power consumption has already become a real design issue. Especially, excessive leakage power consumption at high temperatures often causes significant product parametric yield drop in reality 1 . Thus, DVS methods need to optimize leakage energy as well as switching energy.In order to reduce leakage energy consumption, we apply combined V dd /V bs scaling [10][11] since body biasing (scaling V bs ) 1 Although the power consumption specification can be met at room temperature, it cannot often be met due to significant leakage power consumption at high temperatures in the product specifications, e.g. 80 or 125℃.is the most effective way to control leakage power consumption. In our work, we extend the statistical DVS method (which originally targets only dynamic energy) to tackle the reduction of both switching and leakage energy by scaling both V dd and V bs . Note that the statistical method covers the method based on average energy execution path [6] as a simplified case. We give a mathematical formulation of the problem of V dd /V bs scaling based on the statistical information, i.e. the distribution of software runtime. The formulation gives a multi-variable non-linear function of total energy consumption. As a practical solution to obtain the workload estimations for the minimum average energy consumption, we present a numerical solution.This paper is organized as follows. Section 2 reviews existing DVS methods. Section 3 explains the mathematical formulation of statistical DVS based on combined V dd /V bs scaling. Section 4 gives a total power function for combined V dd /V bs scaling. Section 5 presents a numerical solution to the problem. Section 6 reports experimental results and Section...
-In this work, we propose a SoC power estimation framework built on our system-level 1 simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design.
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