Resumen. tiva 0 la formación para la adquisición de la cultura emprendedora se constituye como uno de los pilares centrales que deben guiar las políticas educativas de los países europeos. Con el RD 1147/2011, de 29 de julio, se introdujo el módulo profesional de empresa e iniciativa emprendedora. También la Ley 14/2013, de 27 de septiembre de apoyo a los emprendedores y su internacionalización, incorpora medidas para que los jóvenes adquieran, a través del sistema educativo, las competencias y habilidades requeridas para emprender.
This paper is intended as an exploration of university faculty and students' perceptions of a number of dimensions involved in the written composition of academic texts. We analysed the responses to scale 3 in the European Writing Survey (EUWRIT) (in its Spanish version: Encuesta Europea sobre la Escritura Académica, EEEA) by a group of social science and humanities students (n = 1,030) and faculty (n = 230) from nine Spanish universities. We then examined the similarities and differences in their perceptions and established a factorial structure of the different dimensions underlying the writing process. The data indicate that both groups concur in the value assigned to both changing ideas in the course of the composition process (although this process seems to be understood differently by each group) and the revision and feedback processes. The students, however, claim to be involved in more planning and previous reading activities than the teachers perceive them to be. The significance of these results for a processoriented perspective in academic writing is discussed.
This thesis work and my degree would not have been possible without the help and support of my advisor, Dr. Sonia López Alarcon. Her guidance has helped me grow as a student and researcher, providing the foundation for the rest of my academic career. Without the feedback from my committee members, Dr. Muhammad Shaaban and Dr. Khireesha Kudithipudi, this document and my degree would not have been finished. I would also like to thank Dr. Julio Sahuquillo Borrás for his invaluable help while living across an ocean. A thanks to Paul Mezzanini in Research Computing, without his resources I would not be able to have the comprehensive results that I have, and who raised the priority of my jobs so I could get results when it mattered. I would also like to thank Dave Warth, my track coach and friend who helped to teach me how to be mentally strong. Finally, I would like to thank the Computer Engineering department for putting up with me for so many years. v
The spectral broadening of the pump pulse through self phase modulation in a time domain distributed Brillouin sensor is demonstrated to have a non-negligible detrimental effect, leading to a doubling of the effective gain linewidth after some 20 km in standard conditions. The theoretical modeling is fully confirmed by experimental results.
Los modelos de predicción de la insolvencia empresarial se han fundamentado en el comportamiento de un conjunto de variables económico-financieras, y otras relativas a las características de la empresa, centrados en grandes empresas. Este trabajo analiza la aplicación de un modelo a empresas de diferente tamaño, estudiando de forma especial el comportamiento de las sociedades cooperativas. Para ello, se analiza la capacidad predictiva del modelo sobre el posible fracaso empresarial, constituyéndose la solvencia, la liquidez y la rentabilidad como las principales variables para anticipar esta situación. Por otra parte, se incluye el posible efecto moderador de la forma jurídica de sociedad cooperativa en ambas variables, para determinar si las particularidades derivadas de su proyección social suponen un efecto diferenciador.
En este contexto, se estudia la percepción del emprendimiento, y de las empresas de trabajo asociado, entre los jóvenes universitarios de la Universidad Complutense de Madrid, así como las iniciativas que se están llevando a cabo desde esta institución para fomentar, difundir y apoyar estas iniciativas emprendedoras.
One of the main challenges of using heterogeneous systems results from the need to find the computationto-hardware assignments that maximize the overall application performance. The important computational factors that must be taken into account include algorithmic complexity, exploitable parallelism, memory bandwidth requirements, and data size. To achieve high performance, a hardware platform is chosen to satisfy the needs of a computation with corresponding architectural features such as clock speed, number of parallel computational units, and memory bandwidth. In this paper five linear algebra computations that are commonly found in compute-intensive applications are selected and evaluated in terms of performance on CPU, GPU, and FPGA platforms across a wide range of data sizes. The results are used to provide guidelines to help select the best performing hardware platform based on the computational factors. Using a cutting edge signal processing application as a case study, we demonstrate the importance of making computation assignments for improved performance. Our experimental results show that a properly implemented heterogeneous system achieves a speedup of up to 39x and 3.8x compared to CPU-only and GPU-only systems respectively.978-1-4799-0493-8/13/$31.00
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same application, may require a different capacity-speed tradeoff. This problem is exacerbated in a Simultaneous Multi-Threaded (SMT) processor where the optimal cache design may vary drastically with the number of running threads and their characteristics.We propose to make this capacity-speed cache tradeoff dynamic within an SMT core. We extend a previously proposed globally asynchronous, locally synchronous (GALS) processor core with multi-threaded support, and implement dynamically resizable instruction and data caches. As the number of threads and their characteristics change, these adaptive caches automatically adjust from small sizes with fast access times to higher capacity configurations. While the former is more performance-optimal when the core runs a single thread, or a dual-thread workload with modest cache requirements, higher capacity caches work best with most multiple thread workloads. The use of a GALS microarchitecture permits the rest of the processor, namely the execution core, to run at full speed irrespective of the cache speeds. This approach yields an overall performance improvement of 24.7% over the best fixed-size caches for dual-thread workloads, and 19.2% for single-threaded applications.
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