In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths selected with a criterion. While the proposed method generates each two-pattern test for more than one fault in the target fault list as well as ordinary test compaction methods, secondary target faults are selected from the fault list such that many other faults, which may not be included in the fault list, are detected by the test pattern. Even if faults on long paths in a manufactured circuit are not included in the fault list due to a process variation or noise, the compact test set would detect the longer untargeted faults, i.e., the test set has a noise or variation tolerant nature. Experimental results show that the proposed method can generate a compact test set and it detects longer untargeted path delay faults efficiently.
To reduce VLSI turnaround t i m e and c o s t , an e f f i c i e n t f a u l t d i a g n o s i s method must be developed.Electron-beam probing, which allows observation of t h e s i g n a l values w i t h i n a chip, i s one of t h e promising approaches f o r f a u l t diagnosis. However, i t i s s t r o n g l y d e s i r e d t h a t t h e number of probes be reduced; otherwise, a g r e a t d e a l of e f f o r t r e s u l t s . The electron-beam probing, guided by deduction based on i m p l i c a t i o n s of i n t e r n a l s i g n a l v a l u e s [ 6 ] , i s considered one of t h e e f f e c t i v e s o l u t i o n s t o t h i s problem. Here t h i s idea i s b u i l t upon by adding preprocessing t o f u r t h e r reduce t h e number of probes and postprocessing t o improve t h e diagnosis r e s o l u t i o n . The method proposed e f f i c i e n t l y diagnoses m u l t i p l e stuck-at f a u l t s i n combinational c i r c u i t s . Using computational experiments i t i s a l s o shown t h a t almost a l l of t h e f a u l t s are diagnosed by probing about 15 p e r c e n t of t h e n e t s when t e s t p a t t e r n s f o r d e t e c t i n g s i n g l e stuck-at f a u l t s are used. 1. I n t r o d u c t i o n Although more and more d i f f e r e n t kinds of VLSI products are being produced, t h e small volume of each type demands development of an e f f i c i e n t f a u l t d i a g n o s i s method i n o r d e r t o reduce both turnaround t i m e and cost. I n t h e development phase t h e capabili t y t o diagnose m u l t i p l e f a u l t s is e s p e c i a ll y d e s i r e d . A number of d i a g n o s i s methods have s o f a r been proposed. However, each h a s some p r a c t i c a l use problems. I n t h e f a u l t dic-21 t i o n a r y method, which s t o r e s t h e abnormal o u t p u t s f o r v a r i o u s f a u l t s i n a d i c t i o n a r y and compares them a g a i n s t t h e observed outp u t s [ 11 , t h e s i z e of t h e d i c t i o n a r y becomes very l a r g e when t h e c i r c u i t s become l a r g e . When m u l t i p l e f a u l t s are considered, t h i s problem becomes prominent and i t i s not p r a c t i c a l . The cause-effect a n a l y s i s method [ 2 ] , i n which f a u l t s are i n f e r r e d from t h e observed o u t p u t v a l u e s without u s i n g a d i c t i o na r y , does not g u a r a n t e e maximum r e s o l u t i o n . which can be probed a t one t i m e i s l i m i t e d , a c o n s i d e r a b l e amount of t i m e i s necessary t o probe a l l of t h e n e t s . Moreover, probing n e t s t h a t are not on t h e t o p l a y e r r e q u i r e s much e f f o r t . A method combining t h e b a s i c o p e r a t i o n of t h e c a u s e -e f f e c t a n a l y s i s method and t h e probing [ 6 ] seems t o have t h e p o s s i b i l i t y of becoming a n e f f i c i e n t diagn o s i s method. r e q u i r e d . c u i t s based on previous r e s e a r c h [ 6 ] and by adding t o i t a preprocessing t o reduce t h e number of probes and a postprocessing ...
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