Metal‐assisted etching is used in conjunction with block‐copolymer lithography to create ordered and densely‐packed arrays of high‐aspect‐ratio single‐crystal silicon nanowires with uniform crystallographic orientations. Nanowires with diameters and spacings down to 19 nm and 10 nm, respectively, are created as either continuous carpets or as carpets within trenches. Wires with aspect ratios up to 220 are fabricated, and capillary‐induced clustering of wires is eliminated through post‐etching critical point drying. The wires are single crystals with 〈100〉 axis directions. The distribution of wire diameters is narrow and closely follows the size distribution of the block copolymer, with a standard deviation of 3.12 nm for wires of mean diameters 22.06 nm. Wire arrays formed in carpets and in channels have hexagonal order with good fidelity to the block copolymer pattern. Fabrication of wires in topographic features demonstrates the ability to accurately control wire placement. Wire arrays made using this new process will have applications in the creation of arrays of photonic and sensing devices.

A systematic study of metal‐catalyzed etching of (100), (110), and (111) silicon substrates using gold catalysts with three varying geometrical characteristics: isolated nanoparticles, metal meshes with small hole spacings, and metal meshes with large hole spacings is carried out. It is shown that for both isolated metal catalyst nanoparticles and meshes with small hole spacings, etching proceeds in the crystallographically preferred <100> direction. However, the etching is confined to the single direction normal to the substrate surface when a catalyst meshes with large hole spacings is used. We have also demonstrated that the metal catalyzed etching method when used with metal mesh with large hole spacings can be extended to create arrays of polycrystalline and amorphous vertically aligned silicon nanowire by confining the etching to proceed in the normal direction to the substrate surface. The ability to pattern wires from polycrystalline and amorphous silicon thin films opens the possibility of making silicon nanowire array‐based devices on a much wider range of substrates.