A 24-GHz transformer-based stacked-FET power amplifier (PA) was designed in 90-nm CMOS technology. The stack configuration overcomes the low breakdown voltages of scaled transistors. The proposed power amplifier achieves a saturated output power of 21.7 dBm and 1-dB compressed output power (OP 1dB ) of 18.9 dBm with peak power-added efficiency (PAE) of 16.7% at 3-V supply voltage. The chip occupies an area of 0.53 × 0.51 mm 2 , including all the dc and RF pads.
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