Latency, caused by remofe memo y access and remote procedure call, is one of the most serious problems in massively parallel computers. In order to eliminate the processors' idle time caused by these latencies, processors must perform fast context switching among fine-grain concurrent processes.In this paper, we propose a processor architecture, called Datarol-11, that promotes eficient finegrain multi-thread execution by performing fast context switching among fine-gram concurrent processes. In the Datarol-11 processor, an implicit register load/store mechanism is embedded in the execution pipeline in order to reduce memo y access overhead caused by contezt switching. In order to reduce local memory access latency, a two-level hierarchical memory system and a load control mechanism are also introduced. We describe the Datarol-11 processor architecture, and show ifs evaluation results.
This is the first work in its type trying to optimize the set of controls for a state feedback. Controlled Dan/Petri nets + is a modeling framework based on Place/Transitions Nets used to model a control-logic called multiple and simultaneous control (MSC) which can reduce the size of the set of controls. In this paper we present the subnet structure called Σ f(q) to model the MSC-logic and an algorithm to design an optimal state feedback with a set of controls for a class of Dan/Petri Net + having a single-place connected circuits and the conditions to obtain a maximally permissive and optimal state feedback.
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