Abstract. We construct an individual-based kinematic model of rolling migratory locust swarms. The model incorporates social interactions, gravity, wind, and the effect of the impenetrable boundary formed by the ground. We study the model using numerical simulations and tools from statistical mechanics, namely the notion of H-stability. For a free-space swarm (no wind and gravity), as the number of locusts increases, it approaches a crystalline lattice of fixed density if it is H-stable, and in contrast becomes ever more dense if it is catastrophic. Numerical simulations suggest that whether or not a swarm rolls depends on the statistical mechanical properties of the corresponding free-space swarm. For a swarm that is H-stable in free space, gravity causes the group to land and form a crystalline lattice. Wind, in turn, smears the swarm out along the ground until all individuals are stationary. In contrast, for a swarm that is catastrophic in free space, gravity causes the group to land and form a bubble-like shape. In the presence of wind, the swarm migrates with a rolling motion similar to natural locust swarms. The rolling structure is similar to that observed by biologists, and includes a takeoff zone, a landing zone, and a stationary zone where grounded locusts can rest and feed.
The power density of modern ICs continues to increase with each new process technology. Larger power density blocks result in higher temperatures which in turn decrease the reliability of chips and produce more leakage power. In this paper we present a method to help reduce the temperature of chips at the floorplan design level by adjusting block utilizations based on the available whitespace in a floorplan. We also briefly outline a method for fast and accurate thermal floorplanning. Our experimental results show that peak IC temperatures can be significantly reduced at the floorplan design stage by using the aforementioned methods without sacrificing significant increases in floorplanning run-time, or wirelength.
Abstract-Power supply C4 (flip-chip) bonds are susceptible to failures due to electro-migration caused by high on-chip temperatures, large currents and manufacturing variability. A single C4 bond failure can result in catastrophic failures in the power supply network and thus redundant bonds are naively added to the circuit to mitigate the impact of bond failures. We propose a method for improved redundant bond placement using an Integer Linear Program (ILP) that reduces the required number of redundant bonds by 33% while ensuring power supply integrity in the presence of a single-bond failure.
The magnitude of the I/O requirements for modern ICs continues to increase due to the growing complexity and size of ICs. The large I/O count found on most ICs have forced most designers to use flip-chip packaging instead of wire bonded packaging. Unfortunately, the solder bumps in flip-chip packages are susceptible to failure, especially in the presence of high temperatures which can cause large stresses and strains leading to mechanical failure of the bump. In this paper, we present a simplified stress/strain/fatigue model that can be used during floorplanning to optimize for package reliability. We also demonstrate a quadratic C4 bump placement method that can be used during floorplanning to increase C4 bump reliability. Our experimental results show that this co-optimization can increase the lifetime of C4 bumps by about 47× with only a modest 3% increase in HPWL wirelength.
Abstract-Power Supply Networks (PSN) are susceptible to electromigration failure and increased resistance due to high on-chip temperatures and large power supply currents. Joule heating, which leads to increased localized interconnect temperatures and higher resistivity in the PSN interconnect, exacerbates this reliability problem and is only expected to worsen in future technologies. The best method of reducing interconnect Joule heating is by reducing the RMS current within the interconnect. Consequently, we propose the first gradient-based decoupling capacitance placement method to reduce the magnitude of the current spikes in the interconnect. Our experiments show that our propose approach can reduce interconnect temperatures by 12.5 K which results in a 4.7% decrease in resistivity and an increase of 66.3% in electromigration lifetime.
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