Package-chip co-design to increase flip-chip C4 reliability

Abstract

The magnitude of the I/O requirements for modern ICs continues to increase due to the growing complexity and size of ICs. The large I/O count found on most ICs have forced most designers to use flip-chip packaging instead of wire bonded packaging. Unfortunately, the solder bumps in flip-chip packages are susceptible to failure, especially in the presence of high temperatures which can cause large stresses and strains leading to mechanical failure of the bump. In this paper, we present a simplified stress/strain/fatigue model that can be used during floorplanning to optimize for package reliability. We also demonstrate a quadratic C4 bump placement method that can be used during floorplanning to increase C4 bump reliability. Our experimental results show that this co-optimization can increase the lifetime of C4 bumps by about 47× with only a modest 3% increase in HPWL wirelength.