Spray cooling is implemented on an engineering tool for Time Resolved Emission measurements using a silicon solid immersion lens to achieve high spatial resolution and for probing high heat flux devices. Thermal performance is characterized using a thermal test vehicle consisting of a 4x3 array of cells each with a heater element and a thermal diode to monitor the temperature within the cell. The flip-chip packaged TTV is operated to achieve uniform heat flux across the die. The temperature distribution across the die is measured on the 4x3 grid of the die for various heat loads up to 180 W with corresponding heat flux of 204 W/cm2. Using water as coolant the maximum temperature differential across the die was about 30 °C while keeping the maximum junction temperature below 95 °C and at a heat flux of 200 W/cm2. Details of the thermal performance of spray cooling system as a function of flow rate, coolant
For time resolved hot carrier emission from the backside, an alternate approach is demonstrated termed single point PICA. The single point approach records time resolved emission from an individual transistor using time-correlated-single-photon counting and an avalanche photo-diode. The avalanche photo-diode has a much higher quantum efficiency than micro-channel plate photo-multiplier tube based imaging cameras typically used in earlier approaches. The basic system is described and demonstrated from the backside on a ring oscillator circuit.
A new tool (Schlumberger IDS 2000) has become available for acquiring waveforms from C4 (also known as flip chip) packaged IC’s. The waveform acquisition technique is based on electro-optic sampling through the backside of silicon. After explaining the physics of electro-optic sampling, the technique is demonstrated through the backside of Si on a simple diode test structure and a flip chip microprocessor. Also, many of the issues and challenges with this tool are discussed.
Traditional microprobing on conventional wirebonded packages is difficult on sub-micron feature sizes. The problem becomes even more complex with flip-chip packaged devices as access to circuitry is limited because of the substrate silicon. We describe here an Atomic Force Microscope (AFM) based tool for microprobing that we term “nanoprobing” because of the feature sizes that can be probed with this tool. Three applications have been described here where voltage levels or waveforms are measured. These include probing on: A single metal-layer test chip that is wire-bonded to a 40-pin DIP package, a 3-layer CMOS circuit that is wire bonded to a 48 pin DIP package, and a 5-metal layer CMOS circuit that is flip chip packaged to a 321 pin PGA package.
With the ever-increasing density and performance of integrated circuits, non-invasive, accurate, and high spatial and temporal resolution electric signal measurement instruments hold the key to performing successful diagnostics and failure analysis. Sampled electrostatic force microscopy (EFM) has the potential for such applications. It provides a noninvasive approach to measuring high frequency internal integrated circuit signals. Previous EFMs operate using a repetitive single-pulse sampling approach and are inherently subject to the signal-to-noise ratio (SNR) problems when test pattern duty cycle times become large. In this paper we present an innovative technique that uses groups of pulses to improve the SNR of sampled EFM systems. The approach can easily provide more than an order of magnitude improvement to the SNR. The details of the approach are presented.
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