As the scaling trend becomes accelerated in process technology for cost reduction in semiconductor chip manufacturing, the requirement for shrink technology has increased. Hot Carrier Injection (HCI) degradation for I/O transistors is most concerning part when shrink. To solve this, the effective channel length (Leff) was increased using liner oxide before Light Doped Drain (LDD) implants and optimized the tilt angle to increase Leff without E-field degradation in LDD region, satisfying the HCI specification.

Defect generation during organic bottom anti-reflective coating (BARC) in the photo lithography process is closely related to humidity control in the BARC coating unit. Defects are related to the water component due to the humidity and act as a blocking material for the etching process, resulting in an extreme pattern bridging in the subsequent BARC etching process of the poly etch step. In this paper, the lower limit for the humidity that should be stringently controlled for to prevent defect generation during BARC coating is proposed. Various images of defects are inspected using various inspection tools utilizing optical and electron beams. The mechanism for defect generation only in the specific BARC coating step is analyzed and explained. The BARC defect-induced gate pattern bridging mechanism in the lithography process is also well explained in this paper.

In this paper, a carbon implant is investigated in detail from the perspectives of performance advantages and side effects for the thick n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET). Threshold voltage (Vth) adjustment using a carbon implant significantly improves the Vth mismatch performance in a thick (3.3-V) n-MOS transistor. It has been reported that a bad mismatch occurs particularly in the case of 0.11-μm Vth node technology. This paper investigates a carbon implant process as a promising candidate for the optimal Vth roll-off curve. The carbon implant makes the Vth roll-off curve perfectly flat, which is explained in detail. Further, the mechanism of hot carrier injection lifetime degradation by the carbon implant is investigated, and new process integration involving the addition of a nitrogen implant in the lightly doped drain process is offered as its solution. This paper presents the critical side effects, such as Isub increases and device performance shifts caused by the carbon implant and suggests an efficient method to avoid these issues.

This paper relates 10% shrink from 0.13㎛ design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor (1.2fF/㎛2) was developed and its performance were evaluated.

본 논문은 기존의 poly length만의 축소와 달리 입, 출력 소자를 포함한 core 디바이스의 0.13㎛ 디자인을 10% 축소하는 것으로 여러 채널 길이에 따른 body effect와 doping profile simulation을 해석하였다. 축소 전 의 DC 파라미터 매칭을 위하여 게이트 산화막의 decoupled plasma nitridation 처리와 LDD(Lightly Doped Drain) 이온주입 전 TEOS(Tetraethylortho silicate) 산화막 100Å 그리고 LDD 이온주입을 22o tilt-angle(45o twist-angle)로 최적화하였고 그 결과 축소 전의 5%의 범위에서 매칭됨을 확인하였다.ABSTRACT This paper relates 10% shrink from 0.13㎛ design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide 100Å before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.