This paper proposes an equivalent circuit model of 3-D DRAM cell transistors with recess gate and saddle fin structure for the first time. The model effectively characterize the sub-threshold and off margin behavior of the scaled DRAM cell transistor by considering the parasitic sub-channel and vertical transistor components into account. TCAD simulation and experimental data have confirmed the accuracy of the model. With the analysis made, we suggest a set of improvement method for the off margin characteristics engineering. These methods are believed to lead the continuous DRAM scaling, down to sub10nm technology node.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.