Study on the Sub-Threshold Margin Characteristics of the Extremely Scaled 3-D DRAM Cell Transistors

Abstract

This paper proposes an equivalent circuit model of 3-D DRAM cell transistors with recess gate and saddle fin structure for the first time. The model effectively characterize the sub-threshold and off margin behavior of the scaled DRAM cell transistor by considering the parasitic sub-channel and vertical transistor components into account. TCAD simulation and experimental data have confirmed the accuracy of the model. With the analysis made, we suggest a set of improvement method for the off margin characteristics engineering. These methods are believed to lead the continuous DRAM scaling, down to sub10nm technology node.

Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application

“…Also, the buried gate can be constructed by an etch-back process after the chemical mechanical polishing (CMP) of the gate metal as shown in Fig. 2(e) [18,19]. The buried gate structure is essential to alleviate the capacitive coupling between the source/drain and the IM in RC-FeMFET.…”