Memristive switching devices are promising for future data storage and neuromorphic computing applications to overcome the scaling and power dissipation limits of classical CMOS technology. Many groups have engineered bilayer oxide structures to enhance the switching performance especially in terms of retention and device reliability. Here, introducing retention enhancement oxide layers into the memristive stack is shown to result in a reduction of the switching speed not only by changing the voltage and temperature distribution in the cell, but also by influencing the rate‐limiting‐step of the switching kinetics. In particular, it is demonstrated that by introducing a retention enhancement layer into resistive switching SrTiO3 devices, the kinetics are no longer determined by the interface exchange reaction between switching oxide and active electrode, but depend on the oxygen ion migration in the additional interface layer. Thus, the oxygen migration barrier in the additional layer determines the switching speed. This trade‐off between retention and switching speed is of general importance for rational engineering of memristive devices.
Memristive devices are novel electronic devices, which resistance can be tuned by an external voltage in a non-volatile way. Due to their analog resistive switching behavior, they are considered to emulate the behavior of synapses in neuronal networks. In this work, we investigate memristive devices based on the field-driven redox process between the p-conducting Pr0.7Ca0.3MnO3 (PCMO) and different tunnel barriers, namely, Al2O3, Ta2O5, and WO3. In contrast to the more common filamentary-type switching devices, the resistance range of these area-dependent switching devices can be adapted to the requirements of the surrounding circuit. We investigate the impact of the tunnel barrier layer on the switching performance including area scaling of the current and variability. Best performance with respect to the resistance window and the variability is observed for PCMO with a native Al2O3 tunnel oxide. For all different layer stacks, we demonstrate a spike timing dependent plasticity like behavior of the investigated PCMO cells. Furthermore, we can also tune the resistance in an analog fashion by repeated switching the device with voltage pulses of the same amplitude and polarity. Both measurements resemble the plasticity of biological synapses. We investigate in detail the impact of different pulse heights and pulse lengths on the shape of the stepwise SET and RESET curves. We use these measurements as input for the simulation of training and inference in a multilayer perceptron for pattern recognition, to show the use of PCMO-based ReRAM devices as weights in artificial neural networks which are trained by gradient descent methods. Based on this, we identify certain trends for the impact of the applied voltages and pulse length on the resulting shape of the measured curves and on the learning rate and accuracy of the multilayer perceptron.
A controlled reference circuit maintains the output voltage levels and current values of an LVDS output buffer constant over (PVT) processing, voltage supply, and temperature variations. The reference circuit requires one external resistor and generates two DC control voltages which are applied to all output buffers. An on-chip resistance is described which maintains a tightly controlled impedance of approximately 10052 over the common mode range of 0 to 2.4V. A measured waveform at 1.244GbIs is given.
The caption states the potentiation and depression observed in Fig. 21a and 21b respectively are for separate devices with different composition. Is it that each device exhibits only one of the behaviours shown or do the two devices exhibit both potentiation and depression as well? Also, what is the retention time of this potentiation and depression? Hyunsang Hwang responded: Thank you for your comment. It was a typo. We measured potentiation and depression using a Mo/TiO x /TiN device. I will revise the manuscript. Although we did not perform an in-depth study on retention characteristics, we cannot guarantee long-term retention using the Mo/TiO x /TiN device. Hyunsang Hwang answered: Thank you for your comments. I agree with your comments. We consider I-V linearity to implement matrix multiplication using an analog input voltage. If we cannot meet ideal I-V linearity, we can integrate the read current with multiple pulses which require additional circuits.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.