With ever-decreasing CMOS transistor sizes, integrated circuits are becoming more and more susceptible to errors. A commonly used approach to improve the reliability of digital circuits is triple modular redundancy (TMR). TMR instantiates three copies of a circuit plus additional voter circuits to take majority decisions on the output values. Prior research has studied variations in TMR voting structures that bring about improvements in performance factors such as area utilization, power consumption and latency at the price of slight degradation in output reliability. In this paper, we extend previous studies by utilizing different redundancy configurations and voter-insertion algorithms to observe variation in these performance factors for FPGA designs. To maintain an automated tool flow for redundancy insertion into a digital design, we enhance the functionality of the previous BYU-LANL TMR tool to include alternative TMR and cascaded TMR redundancy configurations. Design space exploration experiments with different ISCAS circuit benchmarks show that the choice of an appropriate redundancy configuration and voter-insertion algorithm has a strong impact on optimizing performance factors. To support a designer with selecting a redundant implementation, we present a design space exploration tool flow that takes a circuit as input and identifies Paretooptimal implementations with respect to the four objectives reliability level, utilized FPGA area, latency and dynamic power consumption.
Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.
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