Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection

Meisner, Sebastian; Platzner, Marco

doi:10.1007/978-3-319-05960-0_30

Cited by 3 publications

(2 citation statements)

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“…Meisner and Platzner [61] investigate using a hybrid multi-core, which combines "normal" cores with cores that are implemented in a field-programmable gate array (FPGA). They propose a dynamic redundancy technique, named thread shadowing, which duplicates (shadows) a software or hardware thread during a time period.…”

Section: Fault Tolerance Methodsmentioning

confidence: 99%

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Timing Predictability in Future Multi-Core Avionics Systems

Löfwenmark¹

2017

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With more functionality added to safety-critical avionics systems, new platforms are required to offer the computational capacity needed. Multi-core platforms offer a potential that is now being explored, but they pose significant challenges with respect to predictability due to shared resources (such as memory) being accessed from several cores in parallel. Multi-core processors also suffer from higher sensitivity to permanent and transient faults due to shrinking transistor sizes.This thesis addresses several of these challenges. First, we review major contributions that assess the impact of fault tolerance on worst-case execution time of processes running on a multi-core platform. In particular, works that evaluate the timing effects using fault injection methods. We conclude that there are few works that address the intricate timing effects that appear when inter-core interferences due to simultaneous accesses of shared resources are combined with the fault tolerance techniques. We assess the applicability of the methods to COTS multi-core processors used in avionics. We identify dark spots on the research map of the joint problem of hardware reliability and timing predictability for multi-core avionics systems.Next, we argue that the memory requests issued by the real-time operating systems (RTOS) must be considered in resource-monitoring systems to ensure proper execution on all cores.We also adapt and extend an existing method for worst-case response time analysis to fulfill the specific requirements of avionics systems. We relax the requirement of private memory banks to also allow cores to share memory banks.

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Section: Fault Tolerance Methodsmentioning

confidence: 99%

“…The most common surveyed method for detecting and recovering from faults is process redundancy or re-execution [44,61,[64][65][66]86]. Redundancy is particularly relevant when it comes to multi-core platforms, since plenty of resources exist for execution.…”

Section: (Question 1 and 2)mentioning

confidence: 99%