IntroductionA high performance 0.20pm logic technology has been developed with six levels of planarized copper interconnects. 0.15pm transistors (Lg,,,=0.15+0.04pm) are optimized for 1.8V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized in Table 1 and enable fabrication of 7.6pm2 6T SRAM cells.Isolation and Transistors CMP planarized shallow trenches with good electrical isolation down to n+/p+ spacings of 0.5pm were fabricated (Fig. 1). Dual gate 0.15pm transistors with 35A physical gate oxides (accumulation t,,=39A measured at Vg=+l .SV) were formed using super steep retrograde channels, shallow extensions and halos, relatively deep source/drain regions and 1 OOnm nitride spacers. CoSi, was selectively formed on the polysilicon gates and source/drain regions with a nominal sheet resistance of 9Wsq. Rapid thermal processing was utilized as much as possible throughout the flow to minimize transient enhanced dopant diffusion.Fig. 2 shows a typical SEM cross-section of a NMOS transistor with a gate length of 0.15pm. Well delineated shallow S/D extensions and the deeper S/D junctions are clearly observed. The saturation drive currents for nominal gate length NMOS and PMOS devices are shown in Fig. 3 . The nominal drive currents are 630pNpm for NMOS and 230pA/ym for PMOS at 1.8V. The off-state leakage currents of these devices are well below the worst case leakage specification of 2nA/pm. The drain induced barrier lowering (DIBL) measured on NMOS and PMOS devices is plotted as a function of Leff in Fig. 4. Good short channel characteristics are maintained down to effective channel lengths of O.1ym. The Vt roll-off for N and P devices in the linear and saturation regions are shown in Fig. 5. The Vt's are 0.44V and -0.46V for Nch and Pch respectively, at a gate length of 0.15pm and the associated subthreshold slopes are less than 90mv/dec. The use of nitrided gate oxides was investigated due to their superior hot carrier reliability. Fig. 6 compares the degradation under hot carrier stress of nitrided oxides to thermal oxides and highlights the improved reliability of NO-annealed oxides. Peak Gms comparable to those from thermal oxides were obtained (Fig. 7). A further advantage afforded by nitrided gate dielectrics is its superior boron blocking properties, Increasing the poly silicon doping in the P+ gate to reduce poly depletion resulted in only a 88mV Vt shift in nitrided oxides (Fig. 8) compared to a 300mV Vt shift in thermal oxides. A significant reduction in the inversion to, is achieved with the higher gate doping, resulting in improved device characteristics. NMOS transistor design focused on minimizing defect enhanced dopant re-distribution such as TED. To this end, the effect of different source/drain implant energies on NMOS transistor performance is shown in Fig. 9. The lower energy implant results in a significantl...

We present an efficient MOS-capacitor based silicon modulator. In an MZI configuration, a 9dB extinction ratio at 28 Gbps is achieved from the 1V output of a low-power CMOS inverter driver IC.

Electrically tunable photonic band gap ͑PBG͒ structures hold the potential to become a versatile and compact backbone for optical signal processing. In this letter we report electrical tuning of silicon-based two-dimensional PBG structures infiltrated with liquid crystals. An improved electrode configuration is used to avoid electric field screening by the conductive silicon walls. Electrical tuning using fields well below 1 V / m is demonstrated experimentally using both polarized light microscopy and reflectance PBG measurements. The structures can be operated with any electro-optic materials and lead to fast and efficient modulators, routers, and tunable filters.

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Transistor scaling alone can no longer be relied upon to yield the exponential speed increases we have come to expect from the microprocessor industry. The principle reason for this is the interconnect bottleneck, where the electrical connections between and within microprocessors are becoming, and in some cases have already become, the limiting factor in overall microprocessor performance. Optical interconnects have the potential to address this shortcoming directly, by providing an inter- and intrachip communication infrastructure that has both greater bandwidth and lower latency than electrical interconnects, while remaining safely within size and power constraints. In this paper, we review the requirements that a successful optical interconnect must meet, as well as some of the recent work in our group in the area of slow-light photonic crystal devices for on-chip optical interconnects. We show that slow-light interferometric optical modulators in photonic crystal can have not only high bandwidth, but also extremely compact size. We also introduce the first example of a multichannel slow light platform, upon which a new class of ultracompact optical devices can be built.