With increasing chip size and complexity, interconnect delays are becoming limiting factors in increasing performance. 3-D device integration will result in a reduction in chip size and interconnect delay. We present a novel technique for achieving high-performance MOS devices for vertical integration.Poly-Ge is used as a seeding agent to laterally crystallize amorphous Si films into the channel of poly-TFTs, resulting in a substantial performance improvement through a simple, CMOS-compatible process. The technology is scaleable, and should enable near-single crystal performance in deep sub-micron devices.
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