Recently, thin-film transistors (TFTs) have extended their applications to diverse electronics such as flexible/wearable displays, [1-6] health monitoring sensors, [7-10] and artificial neuromorphic devices. [11-13] Particularly, there is growing interest in the display applications for bendable electronics which require high mechanical flexibility, relatively low-temperature processing, and high-resolution device
Here, we demonstrate a side-gated in-plane structure of solution-processed amorphous oxide semiconductor ionotronic devices and logic circuits enabled by ion gel gate dielectrics with a monolithically integrated nanoscale passivation architecture. The large capacitance of the electric double layer (EDL) in the ion gel allows a device structure to be a side gate geometry, forming an in-plane structured amorphous In−Ga−Zn− O (a-IGZO) ionotronic transistor, which can be translated into a simplified logic gate configuration with a low operation voltage. Particularly, the monolithic passivation of the coplanar electrodes offers advantages over conventional inhomogeneous passivation, mitigating unintentional parasitic leakage current through the ion gel dielectric layer. More importantly, the monolithically integrated passivation over electrodes was readily obtained with a complementary metal−oxide semiconductor-compatible photochemical process by employing a controlled ultraviolet light manipulation under ozone ambient, which introduced not only much enhanced electrical characteristics but also a scalable device architecture. We investigated various electrical behaviors of the side-gated a-IGZO ionotronic transistor based on EDL, which is called an electric double layer transistor (EDLT), and logic circuits enabled by photochemically realized monolithic aluminum oxide (AlO X ) passivation comparing to the native or polymerized passivation layer, which reveals that the photoassisted AlO X secures highperformance a-IGZO EDLTs with a low off current (<5.23 × 10 −8 A), high on/off ratio (>1.87 × 10 5 ), and exceptional high carrier mobility (>14.5 cm 2 V −1 s −1 ). Owing to the significantly improved electrical characteristics, an inverter circuit was successfully achieved with broad operation voltages from an ultralow V DD of 1 mV to 1.5 V, showing a fully logical voltage transfer characteristic with a gain of more than 4 V V −1 .
Semiconducting single-walled carbon nanotubes (s-SWCNTs) have gathered significant interest in various emerging electronics due to their outstanding electrical and mechanical properties. Although large-area and low-cost fabrication of s-SWCNT field effect transistors (FETs) can be easily achieved via solution processing, the electrical performance of the solution-based s-SWCNT FETs is often limited by the charge transport in the s-SWCNT networks and interface between the s-SWCNT and the dielectrics depending on both s-SWCNT solution synthesis and device architecture. Here, we investigate the surface and interfacial electro-chemical behaviors of s-SWCNTs. In addition, we propose a cost-effective and straightforward process capable of minimizing polymers bound to s-SWCNT surfaces acting as an interfering element for the charge carrier transport via a heat-assisted purification (HAP). With the HAP treated s-SWCNTs, we introduced conformal dielectric configuration for s-SWCNT FETs, which are explored by a carefully designed wide array of electrical and chemical characterizations with finite-element analysis (FEA) computer simulation. For more favorable gate-field-induced surface and interfacial behaviors of s-SWCNT, we implemented conformally gated highly capacitive s-SWCNT FETs with ion-gel dielectrics, demonstrating field-effect mobility of ~8.19 cm2/V⋅s and on/off current ratio of ~105 along with negligible hysteresis.
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