A differential (or balanced) bandpass filter based on open complementary split ring resonators (OCSRRs) coupled through admittance inverters is presented in this article. Pairs of OCSRRs are symmetrically placed in a mirror configuration between the strips of the differential line and are modeled by means of two series connected parallel resonators. For the differential (odd) mode, there is a virtual ground at the connecting plane between the OCSRR pairs, and the structure is roughly described by the canonical model of a bandpass filter, consisting of a cascade of shunt resonators coupled through admittance inverters. It is demonstrated that, through a proper design of the OCSRR stages, the common mode noise in the vicinity of the differential filter pass band can be efficiently suppressed. Due to the differential mode operation of the filter, it is not necessary to incorporate metallic vias to ground the OCSRRs. Moreover, as compared to other differential filters based on OCSRRs, defected ground structures are not present in the proposed filters. To illustrate the potential of the approach, two balanced bandpass filters are designed, fabricated, and characterized. V C 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:910-916, 2014; View this article online at wileyonlinelibrary.com.ABSTRACT: A dual narrow band wearable antenna is proposed to operate in the range of 2.4-2.5 GHz and 5.7-5.9 GHz for WLAN and telemedicine applications. The proposed design is achieved by simple modification to the rectangular patch antenna. The antenna design is low profile and easy to integrate with the fabric. V C 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:916-918, 2014; View this article online at wileyonlinelibrary.com.
High-performance thin-film transistors (TFTs) are the fundamental building blocks in realizing the potential applications of the next-generation displays. Atomically controlled superlattice structures are expected to induce advanced electric and optical performance due to two-dimensional electron gas system, resulting in high-electron mobility transistors. Here, we have utilized a semiconductor/insulator superlattice channel structure comprising of ZnO/Al2O3 layers to realize high-performance TFTs. The TFT with ZnO (5 nm)/Al2O3 (3.6 nm) superlattice channel structure exhibited high field effect mobility of 27.8 cm2/Vs, and threshold voltage shift of only < 0.5 V under positive/negative gate bias stress test during 2 hours. These properties showed extremely improved TFT performance, compared to ZnO TFTs. The enhanced field effect mobility and stability obtained for the superlattice TFT devices were explained on the basis of layer-by-layer growth mode, improved crystalline nature of the channel layers, and passivation effect of Al2O3 layers.
In this study, amorphous silicon-zinc-tin-oxide thin film transistors (a-SZTO TFTs) are fabricated by radio-frequency magnetron sputtering at room temperature, and the influence of various channel thicknesses on their electrical performance and stability is report. Under the negative bias temperature stress, the transfer curve exhibits threshold voltage shift in the negative direction and degradation of subthreshold swing. In addition, the hump effect occurs in the thick channel, which is primarily due to an increase in total trap density from 5.0 Â 10 11 to 3.5 Â 10 12 cm À2 with an increase in the channel layer thickness from 12 to 72 nm. These results agree well with the increase in the bulk trap density because all a-SZTO TFTs have the same interface; therefore, the interface trap density is excluded. Thicker SZTO TFTs show the hump effect, as they have more donor-like states in the shallow level. Furthermore, temperature stress at 300-333 K and the activation energy (E a ) falling rate are calculated for a-SZTO TFTs. The E a falling rate decreases from 0.103 to 0.010 eV V À1 with increasing channel thickness. Consequently, an a-SZTO TFT with a 12-nm channel layer thickness shows a large E a falling rate (0.103 eV V À1 ) and a small threshold voltage shift of 4.74 V without the hump effect and degraded electrical performance.
TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage (V TH ) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (Δ ΔV TH ) increased steadily, with increasing channel thickness. These results can be explained by the total trap density (N T ) increase due to the increase of bulk trap density (N Bulk ) in a-SIZO channel layer.
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