A dual-mode transimpedance amplifier (TIA) is realised in a 0.18 μm CMOS technology for the applications of 1 Gbit/s laser detection and ranging (LADAR) systems. The proposed dual-mode CMOS feedforward TIA consists of a voltage-mode inverter input stage with a feedback resistor, followed by a current-mode common-gate amplifier with a feed-forward technique applied at the gate so as to achieve low noise, low power consumption, high gain and wide bandwidth characteristics simultaneously. The measured results demonstrate 76 dBΩ transimpedance gain, 720 MHz bandwidth for 0.5 pF photodiode capacitance, −26.3 dBm sensitivity for 10 −12 bit error rate and 20.7 mW power dissipation from a single 1.8 V supply.
This letter presents a multi-rate clock and data recovery circuit realized in a standard 65-nm CMOS technology, which operates from 3.125 Gb/s to 22 Gb/s. In order to cover the wide frequency range, a modified four-stage differential ring VCO is exploited, which provides not only the fast tracking ability from its coarse tuning, but also the precise tra cking from its fine tuning. Also, a voltage-regulated active filter is employed to reduce the ripples of the VCO control voltages. It helps to fasten the lock-in time of the proposed CDR circuit and improve the jitter characteristics against PVT variations. Measurements reveal that the CDR chip demonstrates very wide capture range of 3.125 ∼ 22 Gb/s, 3.3 ps ,rms data jitter at 20 Gb/s, and 112-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 0.12 mm 2 only.
This paper introduces a four-channel optical receiver array implemented in a standard 1P4M 0.18 µm CMOS technology for the applications of active optical HDMI cables. Each channel consists of a current-mirror transimpedance amplifier, a five-stage differential limiting amplifier, and an output buffer, demonstrating 81-dBΩ transimpedance gain, 1.8-GHz bandwidth even with 0.5-pF photodiode capacitance, −18.
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