A 3.125-to-22-Gb/s multi-rate clock and data recovery using voltage-regulated active filter

Abstract

This letter presents a multi-rate clock and data recovery circuit realized in a standard 65-nm CMOS technology, which operates from 3.125 Gb/s to 22 Gb/s. In order to cover the wide frequency range, a modified four-stage differential ring VCO is exploited, which provides not only the fast tracking ability from its coarse tuning, but also the precise tra cking from its fine tuning. Also, a voltage-regulated active filter is employed to reduce the ripples of the VCO control voltages. It helps to fasten the lock-in time of the proposed CDR circuit and improve the jitter characteristics against PVT variations. Measurements reveal that the CDR chip demonstrates very wide capture range of 3.125 ∼ 22 Gb/s, 3.3 ps ,rms data jitter at 20 Gb/s, and 112-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 0.12 mm 2 only.

A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop

“…The clock and data recovery (CDR) circuit, critical building block of high speed serial links, is utilised to recover clock and data information from serial data stream in the noisy channel and re-time data signal to the optimal sampling position under low bit error rate (BER) [7,8,9,16,17,18,21]. The conventional phaselocked loop (PLL) based CDR uses a voltage controlled oscillator (VCO) to generate a quadrature clock phase at the data rate of received data sequence, providing a tunable bit rate and convenience of easily integrated for multi-channel serial link application with single frequency tracking loop for reference clock generation avoiding the need for PLLs at each pin reducing the area occupation and power consumption significantly [10,12,22,23,24,25]. The dual-loop phase interpolator (PI) based CDR topology offers the benefits of increased system stability, simple structure, low power, faster acquisition and a lock of jitter peaking compared with a PLL-based CDR that needs a charge pump, an analog filter and VCO to align phase to optimize sampling point [1].…”

A CMOS high-performance inductorless ring VCO with extended monotonic tuning voltage range

“…Multiphase clocks are widely required for wireline and wireless communication systems, e.g., sub-rate clock and data recovery (CDR) circuits [1] and phased-array transceivers [2]. There exist several kinds of reported oscillators which are able to directly generate multiphase clocks, such as rotary travelling-wave oscillators [3], cross-coupled LC oscillators [4], LC-tuned ring oscillators [2] and inductorless ring oscillators [5]. Among them, inductorless ring oscillators are attractive because of the compact layout and no need for complicated inductor modeling.…”