Dual‐mode CMOS feed‐forward transimpedance amplifier for LADARs

Kim, Seung Hoon; Cho, Sang Bock; Park, Sung Min

doi:10.1049/el.2014.2678

Cited by 11 publications

(5 citation statements)

References 3 publications

(3 reference statements)

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“…In Jeong et al 16 a resistive-inductive feedback was utilized to extend the bandwidth by compensating for the effect of the parasitic capacitances of the constituent transistors of the TIA. 24 However, increasing the overall transconductance, G m , requires increasing the device sizes, which is associated with larger parasitic capacitances and in turn degraded bandwidth, an obvious trade-off between the noise figure and the high gain at one side and the bandwidth at the other side. 17 Since the output signal is fed back to the input by means of a shunt resistor in the configuration of Figure 4B, it is accordingly named the resistive-feedback inverter.…”

Section: Previous Workmentioning

confidence: 99%

“…23 It also results in enhancing the sensitivity. 24 However, increasing the overall transconductance, G m , requires increasing the device sizes, which is associated with larger parasitic capacitances and in turn degraded bandwidth, an obvious trade-off between the noise figure and the high gain at one side and the bandwidth at the other side.…”

Section: Previous Workmentioning

confidence: 99%

“…In Nguyen et al 29 the resistive-feedback configuration was adopted in realizing a programmable gain amplifier. In Kim et al 24 the same inverter cell was utilized in realizing a TIA in laser detection and ranging systems. In Hong et al 25 a voltage-mode feedforward TIA was proposed to achieve both higher gain and smaller noise figure, however, at the same bandwidth of the conventional inverter-based TIA.…”

Section: Previous Workmentioning

confidence: 99%

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Design of the CMOS inverter‐based amplifier: A quantitative approach

Sharroush

2019

Circuit Theory & Apps

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The CMOS inverter can be used as an amplifier if properly biased in the transition region of its voltage-transfer characteristics (VTC). In this paper, the design of this amplifier is investigated with its merits and demerits illustrated and with the various trade-offs involved in its design discussed. Specifically, the following performance metrics are discussed quantitatively: gain, area, linearity, maximum allowable swing, bandwidth, stability, noise factor, impedance matching, and slew rate. Also, the effect of process, voltage, and temperature (PVT) variations are investigated. The optimum number of stages corresponding to the minimum area required for achieving a certain voltage gain is determined. The results obtained from the quantitative analysis and the simulation are discussed.

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Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

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Design of the CMOS inverter‐based amplifier: A quantitative approach

Sharroush

2019

Circuit Theory & Apps

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“…However, modification of the RGC structure in terms of input impedance has been the subject for research to achieve wider bandwidths. Structures such as T-matching network [1], series inductor peaking [2], a capacitive degeneration technique [4], a common-gate feedforward TIA [7], a dual-mode feedforward TIA [8] and a feedforward current amplifier TIA [9] were considered. In terms of 65 *Corresponding Author Institutional Email: abdullahidrees@uomosul.edu.iq (A. I. Mustafa) nm CMOS process technology, various topologies were reported such as an modified RGC TIA using peaking inductors [10], an RGC block and a differential amplifier with active feedback TIA [11] and adjustable gain peaking TIA [12].…”

Section: Introductionmentioning

confidence: 99%

A 65 nm CMOS Feedforward Transimpedance Amplifier for Optical Fibers Communications

Alsheikhjader

Aziz

Mustafa

et al. 2022

IJE

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A series of inductor loads may not be the best design criterion for improvement in circuit performance. In this work, the best compromise so far for the trade-off in power consumption, input referred noise current spectral density, with wide bandwidth, high transimpedance gain and low DC supply voltage is reported. A simulated 65 nm CMOS feedforward transimpedance amplifier is introduced with a series of single PMOS loads instead of a series of inductor loads. A bandwidth of 20.16 GHz with a transimpedance gain of 51.16 dBΩ, an input referred noise current spectral density of 34.3 p A⁄√Hz, a power consumption of 1.052 mW and with a 1V DC supply voltage are presented. In addition, an active inductor load (instead of inductor load) is introduced within the 65 nm CMOS feedforward transimpedance amplifier. A bandwidth of 3.75 GHz with a transimpedance gain of 42.7 dBΩ, an input referred noise current spectral density of 21.4 p A⁄√Hz, a power consumption of 0.66 mW and with a 1V DC supply voltage are reported. This 65 nm CMOS feedforward design process provides enough voltage headrom for gate-to-source terminals in amplifying transistors due to less DC voltage drop across PMOS loads. As a result, this design process consumes the lowest possible power consumption especially with the single PMOS loads as well as with the active inductor load.

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“…Due to the high peak‐to‐average power ratio (PAPR) of the transmitting signals, it is required to manage the trade‐off between efficiency and nonlinear distortions of the power amplifiers (PAs) within these communication systems. Much research has been carried out on PA architectures and linearization technologies to enhance the efficiency and reduce the nonlinear distortion, such as the envelope tracking, the Doherty PA, the feed‐forward PA, and the digital predistortion (DPD) …”

Section: Introductionmentioning

confidence: 99%

A linearized power amplifier with nonlinear feedback architecture

Pan

Quan

et al. 2020

Micro & Optical Tech Letters

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In this letter, a linearized power amplifier (PA) with nonlinear feedback architecture is proposed to improve the linearity of a radio frequency (RF) PA, without efficiency degradation. In this proposed architecture, a linearization circuit is designed for linearity improvement, which consists of a signal cancellation loop and a signal adjustment circuit. The cancellation loop first extracts the distorted signal of the RF PA, while the adjustment circuit regulates the amplitude and the phase of the extracted nonlinear signal before feeding it into the PA with the linear source signal. Subsequently, the regulated nonlinear signal is redirected to the PA input port and combined with the PA input signal to cancel the PA nonlinear distortions. A testbed is designed to validate the performance of the proposed architecture by using the PA chip NPTB00004A at 2.6 GHz with 5‐MHz, 10‐MHz, and 20‐MHz long‐term evolution (LTE) signals. Experimental results show that the proposed architecture can improve the third order intermodulation distortion (IMD3) by more than 30 dB to achieve an adjacent channel power ratio of −45 dBc at an output power level of 33 dBm with drain efficiency over 30%.

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Dual‐mode CMOS feed‐forward transimpedance amplifier for LADARs

Cited by 11 publications

References 3 publications

Design of the CMOS inverter‐based amplifier: A quantitative approach

Design of the CMOS inverter‐based amplifier: A quantitative approach

A 65 nm CMOS Feedforward Transimpedance Amplifier for Optical Fibers Communications

A linearized power amplifier with nonlinear feedback architecture

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