A linearized power amplifier with nonlinear feedback architecture

Abstract

In this letter, a linearized power amplifier (PA) with nonlinear feedback architecture is proposed to improve the linearity of a radio frequency (RF) PA, without efficiency degradation. In this proposed architecture, a linearization circuit is designed for linearity improvement, which consists of a signal cancellation loop and a signal adjustment circuit. The cancellation loop first extracts the distorted signal of the RF PA, while the adjustment circuit regulates the amplitude and the phase of the extracted nonlinear signal before feeding it into the PA with the linear source signal. Subsequently, the regulated nonlinear signal is redirected to the PA input port and combined with the PA input signal to cancel the PA nonlinear distortions. A testbed is designed to validate the performance of the proposed architecture by using the PA chip NPTB00004A at 2.6 GHz with 5‐MHz, 10‐MHz, and 20‐MHz long‐term evolution (LTE) signals. Experimental results show that the proposed architecture can improve the third order intermodulation distortion (IMD3) by more than 30 dB to achieve an adjacent channel power ratio of −45 dBc at an output power level of 33 dBm with drain efficiency over 30%.