Purpose
The solar energy sector has been growing with dramatic reduction in commercial pricing, improved efficiencies and improved deployments/usage conveniences. The purpose of this study is to understand the drivers of the purchase intent for rooftop (RT) solar. This will enable policymakers to improve the penetration of this new and promising green technology.
Design/methodology/approach
This research leverages the framework of unified theory of acceptance and use of technology 2 (UTAUT2) to identify and build a quantitative approach to identify factors (and their relative impact on) the purchase intent of a domestic RT solar buyer. The 400 respondents’ field data were collected in Bangalore (a high RT solar penetration region) and Delhi NCR (relatively lower RT solar penetration region).
Findings
The exploratory factor analysis study revealed that the consumers’ purchase intention of RT Solar is shaped by seven main factors, namely, environmental concerns, social beliefs, hedonic motivation, performance expectancy, price value, self-efficacy and effort expectancy, and that these factors explain 79.2 per cent of the field data. This study finds that social beliefs followed by effort expectance concerns are key factors explaining approximately 20 per cent of the purchase intent each, while unit change in price value beliefs explain about 18 per cent of the purchase intent.
Practical implications
Suggested policy measures include building on strengthening emergence of local solar evangelist groups in the communities and easing effort expectance items (e.g. building legal, regulatory frameworks and financial tools for solar penetration models such as renewable energy services companies).
Originality/value
This paper is the first attempt to model the consumer behavior of the Indian RT solar photovoltaic buyer leveraging the UTAUT2.
Purpose
Rooftop (RT) solar in India has grown to 4.4 GW by the end of March 2019 – but it is still under-performing vs national solar mission target of 40 GW. This paper aims to understand the drivers of the purchase intent (PI) for RT solar will enable policymakers to improve the penetration of this new and promising green technology.
Design/methodology/approach
This paper builds a structural equation modeling model for triggers of the PI of a residential RT solar photo-voltaic (SPV) buyer. The empirical study conducted in Delhi/national capital region of Delhi and Bangalore validates the role of the Unified Theory of Acceptance & Use of Technology (2) constructs in the PI of the residential sector RT solar buyer in India. It also explores a few myths – prior green habits have no relationship with the PI and self-efficacy has been dropped in the final path analysis to improve model fit.
Findings
This research explores the myth that financial self-efficacy – or prospect’s perception of his capability to fund (through own or credit finance) – will mean that the prospect is likely to be more conducive to an SPV purchase in the city contexts studied. It is more relevant for policymakers to work on factors such as social influence/ beliefs, effort expectancy and price-value beliefs. Other relevant triggers are performance expectancy, hedonic motivation and environmental beliefs.
Originality/value
This is the first Indian research leveraging multi-city survey of actual households build an empirically verified consumer behavior model for RT SPV in the residential sector leveraging the unified theory of acceptance and use of technology 2 constructs.
Summary
Major issues in designing low‐power high‐speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field‐effect transistor (FinFET) technology for the design of low‐power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal‐oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2‐, 4‐, 8‐, and 16‐input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK‐DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse‐mesh finite difference (CMFD) technique at a frequency of 200 MHz.
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