a Centre interuniversitaire de recherche sur les réseaux d'entreprise, la logistique et le transport, CIRRELT a Centre interuniversitaire de recherche sur les re´seaux d'entreprise, la logistique et le transport, CIRRELT;The purpose of this article is to help managers early in the design of new product families. Based on product structures, sales forecasts, and constraints imposed by the marketplace, like quality and cost, the proposed method selects the product modules that meet customer requirements for the products, while respecting those constraints. The proposal includes a single-level module design formulation that considers quality and cost simultaneously. The method for testing the proposed algorithm is based on a case study of an electromechanical assembly device (headlamp). The performance of the algorithm is compared to that of the zero module case, where often the constraint problem cannot be resolved. The main result is a model and an algorithm that optimise quality and cost under the constraints of quality and cost. It shows what modules to manufacture, in what quantities, and in which products to use them. The output also provides the predicted quality and cost, based on improvements made to the modules. To conclude, this research enables the joint optimisation of quality and cost by defining the modules to be manufactured. It provides input for managers seeking modules designed for their supply chain. The algorithm provides key input for managing production ramp-up.
International audienceThis article studies the skip, under some assumptions, of process control operations. The case of one tool, one enhanced buffer and one metrology tool of a monotonic parameter is analysed. This article presents circumstances in which control plan can be optimised due to the buffer's behaviour. After discussing the industrial issue of defectivity, this article presents a literature review followed by the model and steps towards industrial development. Then demonstrator, which is applied at a case study of defectivity sampling, is presented. A test of over a 300-mm wafer fabrication data set shows serious improvements - around 35% of defectivity controls have been skipped compared to the static sampling plan
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