Fluctuations have recently been recognized as powerful resources that can be exploited to drive computations, but their use has mostly been limited to logic circuits. This paper goes further and explores a more general framework, in which computation is modeled as a process with a multitude of fluctuating tokens that interact with each other directly or via stigmergy. For the implementation of these concepts Single Electron Tunneling (SET) technology is a strong candidate, since it combines a key element of fluctuation-driven systems, i.e., fluctuating tokens, with the potential for manufacturing in traditional materials (silicon) as well as alternatives, such as molecules. We propose computational elements, i.e., Memory Enhanced Hubs (MEHs), that contain functionality to pass fluctuating signals through them, as well as stigmergic functionality to store a state temporarily and reset it. We introduce a SET based design of such a memory enhance hub instance and demonstrate by means of simulations that it function correctly and that MEHs networks operating according to the stigmergic paradigm can be constructed.
In this paper we present a zero-performanceoverhead online fault detection and diagnosis scheme that exploits the vertical proximity of hardware inherent in 3D stacked integrated circuits (3D-SIC). We consider a 3D stacked processor executing independent instruction streams from different threads, on each die. We propose the vertical clustering of functionally identical computational blocks in order to enable the utilization of the 3D specific low-latency interlayer communication infrastructure. The clustering facilitates the parallel re-execution of instructions on idle units located in the proximity of the units which initially computed them and in this way creates the means for fault diagnosis and detection. We detail the control, interconnection communication infrastructure, instruction distribution, and results processing policies required for our scheme.To determine the effectiveness of the approach, we evaluate its performance in terms of diagnosis latency and percentage of verified operations on 3 to 8 core processors implemented on 3 to 8 tier 3D-SICs, respectively, by means of simulations. Our experiments indicate that the diagnosis latency ranges from 9 to 5 cycles, for 3 to 8 cores, respectively. For transient fault detection our simulations indicate that 86% to 94% of all executed instructions are verified, for 3 to 8 cores, respectively. When only one of the layers is protected against transient faults the number of verified operations increases to 94% to 99%, for the same simulation conditions. This suggests that, if certain conditions are fulfilled at design time, our approach can completely protect one instruction stream identified as being critical for the application. Our simulations clearly indicate that the proposed scheme has the potential to improve the 3D stacked integrated circuits dependability with no performance overhead and at the expense of little area overhead.
This paper presents a set of basic building blocks that corresponds to a universal set of primitives for delay insensitive circuits. We propose single electron tunneling circuit topologies and verify them by means of simulations. The simulations performed with SIMON 2.0 indicate that the circuits function as expected. Moreover the proposed circuits are input-output level compatible thus they can be potentially utilized in the implementation of larger asynchronous circuits. I. BACKGROUNDIt is generally expected that current semiconductor technologies, i.e., CMOS, cannot be pushed beyond a certain limit because of problems arising in the area of power consumption and scalability. A promising alternative to CMOS is Single Electron Tunneling (SET) technology [1], which has the potential of performing computation with much lower power consumption than CMOS and it is scalable to the nanometer region and beyond [2].SET technology is fundamentally different from CMOS as it is based on tunneling of electrons. This difference opens up avenues for new computational paradigms [3,4,5,6], which try to effectively use the basic SET properties. Theoretical results on the complexity of arithmetic operations using those new paradigms indicate great potential. However, electron tunneling is stochastic in nature. Tunneling through a junction becomes possible when the junction's current voltage V j exceeds the junction's critical voltage[7], where q e =1.602*10 -19 C, C j is the capacitance of the junction, and C e is the capacitive value of the remainder of the circuit as seen from the junction. The delay of such circuits cannot be analyzed in the traditional sense. Instead, for each transported electron one can describe the switching delay as, where R t is the junction's resistance and P error is the chance that the desired charge transport has not occurred after t d seconds. This probabilistic delay makes difficult the direct utilization of SET based computation in building synchronous computation units.An alternative solution for SET based computation is to utilize Delay-Insensitive Circuits (DIC), which by their very nature do not require a synchronization signal thus can S. Safiruddin and S.D. Cotofana are with the Computer Eng. Group in TU naturally tolerate the probabilistic behavior of SET circuits. Previous work [9] has already determined a universal set of basic primitives from which, theoretically speaking, any asynchronous circuit can be built. Those primitives are described only at behavioral level and no implementations have been proposed yet. While building blocks to implement the primitives can be potentially constructed in any fabrication technology, CMOS included, there is a natural link between delay insensitive paradigm and SET technology as electrons are a natural way to implement the tokens, which constitute the foundation of delay insensitive computation paradigm. In view of this observation this paper presents SET based implementations of this set of building blocks.To achieve this, delay-insensitive function...
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