Building blocks for delay-insensitive circuits using single electron tunneling devices

Abstract

This paper presents a set of basic building blocks that corresponds to a universal set of primitives for delay insensitive circuits. We propose single electron tunneling circuit topologies and verify them by means of simulations. The simulations performed with SIMON 2.0 indicate that the circuits function as expected. Moreover the proposed circuits are input-output level compatible thus they can be potentially utilized in the implementation of larger asynchronous circuits. I. BACKGROUNDIt is generally expected that current semiconductor technologies, i.e., CMOS, cannot be pushed beyond a certain limit because of problems arising in the area of power consumption and scalability. A promising alternative to CMOS is Single Electron Tunneling (SET) technology [1], which has the potential of performing computation with much lower power consumption than CMOS and it is scalable to the nanometer region and beyond [2].SET technology is fundamentally different from CMOS as it is based on tunneling of electrons. This difference opens up avenues for new computational paradigms [3,4,5,6], which try to effectively use the basic SET properties. Theoretical results on the complexity of arithmetic operations using those new paradigms indicate great potential. However, electron tunneling is stochastic in nature. Tunneling through a junction becomes possible when the junction's current voltage V j exceeds the junction's critical voltage[7], where q e =1.602*10 -19 C, C j is the capacitance of the junction, and C e is the capacitive value of the remainder of the circuit as seen from the junction. The delay of such circuits cannot be analyzed in the traditional sense. Instead, for each transported electron one can describe the switching delay as, where R t is the junction's resistance and P error is the chance that the desired charge transport has not occurred after t d seconds. This probabilistic delay makes difficult the direct utilization of SET based computation in building synchronous computation units.An alternative solution for SET based computation is to utilize Delay-Insensitive Circuits (DIC), which by their very nature do not require a synchronization signal thus can S. Safiruddin and S.D. Cotofana are with the Computer Eng. Group in TU naturally tolerate the probabilistic behavior of SET circuits. Previous work [9] has already determined a universal set of basic primitives from which, theoretically speaking, any asynchronous circuit can be built. Those primitives are described only at behavioral level and no implementations have been proposed yet. While building blocks to implement the primitives can be potentially constructed in any fabrication technology, CMOS included, there is a natural link between delay insensitive paradigm and SET technology as electrons are a natural way to implement the tokens, which constitute the foundation of delay insensitive computation paradigm. In view of this observation this paper presents SET based implementations of this set of building blocks.To achieve this, delay-insensitive function...

Stigmergic search with single electron tunneling technology based memory enhanced hubs

“…This probabilistic delay complicates the direct utilization of SET-based computation in building synchronously timed arithmetic units and since the exact tunnel time of an electron is not known, extensive error correcting schemes are required and switching times have to be lengthy. This has motivated research for SET architectures and circuits based on delayinsensitive computations so that the problems arising from unknown delays are eliminated altogether [11].…”