Enhancing the performance of the voltage source inverters (VSIs) without changing the hardware structure has recently acquired an increased amount of interest. In this study, an optimization algorithm, enhancing the quality of the output power and the efficiency of three-phase grid connected VSIs is proposed. Towards that end, the proposed algorithm varies the switching frequency (f sw ) to maintain the best balance between switching losses of the insulated-gate-bipolar-transistor (IGBT) power module as well as the output power quality under all loading conditions, including the ambient temperature effect. Since there is a contradiction with these two measures in relation to the switching frequency, the theory of multi-objective optimization is employed. The proposed algorithm is executed on the platform of Altera ® DE2-115 field-programmable-gate-array (FPGA) in which the optimal value of the switching frequency is determined online without the need for heavy offline calculations and/or lookup tables. With adopting the proposed algorithm, there is an improvement in the VSI efficiency without degrading the output power quality. Therefore, the proposed algorithm enhances the lifetime of the IGBT power module because of reduced variations in the module's junction temperature. An experimental prototype is built, and experimental tests are conducted for the verification of the viability of the proposed algorithm.

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Many reduced-switch-count (RSC) inverter topologies have been proposed in the literature. As the number of switches required to produce a set of voltages in RSC inverters are less than that in conventional inverter, as a result utilizing RSC inverters in a certain system reduces its size and cost. In this paper, a novel RSC shared inverter topology consisting of fifteen switches and capable of driving four three-phase AC-loads independently is proposed and experimentally verified. A carrier-based pulse width modulation (PWM) technique that employs the zero-sequence-signal injection principle is developed to drive the proposed inverter along with adequate DC voltage bus utilization between the shared loads for common frequency (CF) as well as different frequency (DF) modes. The structure and the principle of operation of the proposed inverter are introduced and intensively verified using simulation and field-programmable-gate-array (FPGA)-in-the-loop simulation under linear and nonlinear loads. Then, Inverter prototype was built and the proposed inverter has been verified experimentally. The experimental results verify the applicability of the proposed inverter and the employed PWM.

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