In this paper, experimental results are shown for a synchronous class-F RF to DC rectifier. The rectifier design is obtained by transforming a class-F amplifier into a rectifier using the theory of time reversal duality. The amplifier and rectifier are tested under identical source power conditions to demonstrate the duality between the circuits. A 10 W Cree HEMT device is used in the designs at a frequency of 985 MHz. The class-F amplifier delivers 8.3 W with an efficiency of 77.5% for a DC source power of 10.7 W. The time reversed dual, a class-F rectifier, delivers 8.7 W of DC load power for a RF input source power of 10.7 W with an efficiency of 81.3%. The rectifier circuit has slightly higher efficiency than the amplifier and lower losses in the rectifier are attributed to device operation in both quadrants I and III compared to an amplifier which operates exclusively in quadrant I. The rectifier has a peak output power of 11.3 W with an efficiency of 78% and this is the highest reported power for a synchronous RF class-F amplifier.
A tracking load circuit for RF rectifiers is described. The tracking load is designed to maximize RF to DC conversion efficiency as the RF input power to the rectifier changes. The circuit consists of two DC to DC converters with two control loops. The duty cycle of the first stage converter is adjusted by an analog control loop to have an input impedance that is optimum for maximizing the power efficiency of the RF rectifier. A second stage converter, either a classical boost or buck converter, converts the fluctuating voltage from the first stage to a regulated output voltage. The application of the tracking load is illustrated with experimental results for a CMOS class D rectifier and a 10 W class F GaN RF rectifier.
Abstract-In this paper, the design of a class-F radio frequency power amplifier with a multiharmonic input transmission line network is presented. Harmonic signal components at the gate come from several sources including nonlinear device capacitances and imperfect output harmonic terminations that create harmonic components that are fed back to the gate through the gate-drain capacitance. The effect of these harmonic generation mechanisms and the potential to shape the gate waveform to improve power efficiency are investigated. The study shows that a second harmonic short is most beneficial and the effect of a third harmonic termination is less significant. The concepts are applied to the design of a 10 W GaN class-F amplifier and the design is supported by theoretical, simulation and experimental results. The fabricated design has a measured drain efficiency of 78.8% at an output power of 40.5 dBm for a frequency of 990 MHz. The amplifier was also tested with a 8.8 dB peak-to-average power ratio 5 MHz WCDMA signal. With the modulated signal, the adjacent channel power ratio was −33.1 dBc at a drain efficiency of 46.1% without predistortion correction.
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