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A method to synthesize the three-dimensional arrangement of bulk tetrahedral MoS2 thin films by solid source chemical vapor deposition of MoO3 and S is presented. The developed synthesizing recipe uses a temperature ramping with a constant N2 gas flow in the deposition process to grow tetrahedral MoS2 thin film layers. The study analyses the time-dependent growth morphologies, and the results are combined and presented in a growth model. A combination of optical, electron, atomic force microscopy, Raman spectroscopy, and X-ray diffraction are used to study the morphological and structural features of the tetrahedral MoS2 thin layers. The grown MoS2 is c-axis oriented 2H-MoS2. Additionally, the synthesized material is further used to fabricate back-gated field-effect transistors (FETs). The fabricated FET devices on the tetrahedral MoS2 show on/off current ratios of 106 and mobility up to ∼56 cm2 V–1 s–1 with an estimated carrier concentration of 4 × 1016 cm–3 for V GS = 0 V.

The proposed study demonstrates a single-step CVD method for synthesizing three-dimensional vertical MoS2 nanosheets. The postulated synthesizing approach employs a temperature ramp with a continuous N2 gas flow during the deposition process. The distinctive signals of MoS2 were revealed via Raman spectroscopy study, and the substantial frequency difference in the characteristic signals supported the bulk nature of the synthesized material. Additionally, XRD measurements sustained the material’s crystallinity and its 2H-MoS2 nature. The FIB cross-sectional analysis provided information on the origin and evolution of the vertical MoS2 structures and their growth mechanisms. The strain energy produced by the compression between MoS2 islands is assumed to primarily drive the formation of vertical MoS2 nanosheets. In addition, vertical MoS2 structures that emerge from micro fissures (cracks) on individual MoS2 islands were observed and examined. For the evaluation of electrical properties, field-effect transistor structures were fabricated on the synthesized material employing standard semiconductor technology. The lateral back-gated field-effect transistors fabricated on the synthesized material showed an n-type behavior with field-effect mobility of 1.46 cm2 V−1 s−1 and an estimated carrier concentration of 4.5 × 1012 cm−2. Furthermore, the effects of a back-gate voltage bias and channel dimensions on the hysteresis effect of FET devices were investigated and quantified.

Hysteresis response of epitaxially grown graphene nanoribbons devices on semi-insulating 4H-SiC in the armchair and zigzag directions is evaluated and studied. The influence of the orientation of fabrication and dimensions of graphene nanoribbons on the hysteresis effect reveals the metallic and semiconducting nature graphene nanoribbons. The hysteresis response of armchair based graphene nanoribbon side gate and top gated devices implies the influence of gate field electric strength and the contribution of surface traps, adsorbents, and initial defects on graphene as the primary sources of hysteresis. Additionally, passivation with AlOx and top gate modulation decreased the hysteresis and improved the current-voltage characteristics.