Hysteresis Associated with Intrinsic-Oxide Traps in Gate-Tunable Tetrahedral CVD-MoS2 Memristor

Kurtash, Vladislav; Mathew, Sobin; Thiele, Sebastian; Scheler, Theresa; Reiprich, Johannes; Hähnlein, Bernd; Stauffenberg, Jaqueline; Manske, Eberhard; Narasimha, Shilpashree; Abedin, Saadman; Jacobs, Heiko O.; Pezoldt, Jörg

doi:10.1109/nano54668.2022.9928717

Cited by 3 publications

(19 citation statements)

References 13 publications

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“…Simulations were performed with parameters based on experimental data stated previously in ref. [12]. In this study, pulses of the following shapes were considered: triangular, rectangular, sinusoidal, and sawtooth.…”

Section: Resultsmentioning

confidence: 99%

“…Simulations were based on the intrinsic-oxide traps model, demonstrated in ref. [12]. According to the theory, intrinsic traps in the active region of the device are associated with grain [16,17], such a combination of trap sources results in clockwise hysteresis when the high resistance state changes into the low resistance state when drain-to-source voltage is applied.…”

Section: Device Dimensions and Simulation Parametersmentioning

confidence: 99%

“…Traps capture probability for both volume and surface traps was fitted using experimental data demonstrated in refs. [12,18].…”

Section: Device Dimensions and Simulation Parametersmentioning

confidence: 99%

“…Simulations were based on the intrinsic‐oxide traps model, demonstrated in ref. [12]. According to the theory, intrinsic traps in the active region of the device are associated with grain boundaries of the

\left(\text{MoS}\right)_{2}

volume.…”

Section: Device Description and Operation Conditionsmentioning

confidence: 99%

“…We present a comprehensive analysis of the electrical characteristics of

\left(\text{MoS}\right)_{2}

memristors based on simulations in terms of the intrinsic‐oxide traps model. [ 12 ] We discuss the influence of various factors, such as the thickness of the

\left(\text{MoS}\right)_{2}

layer, channel length and gate configuration (top or bottom gate), and the applied voltage pulse form on the

\left(\text{MoS}\right)_{2}

memristors hysteresis response. The energy efficiency of different memristor configurations is compared using the ratio of the hysteresis area to the consumed energy.…”

Section: Introductionmentioning

confidence: 99%

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Energy‐Efficient Operation Conditions of MoS₂‐Based Memristors

Kurtash

Jacobs

Pezoldt

2023

Physica Status Solidi (a)

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Sufficient energy consumption for conventional information processing makes it necessary to look for new computational methods. One of the possible solutions to this problem is neuromorphic computations using memristive devices. Memristors based on molybdenum disulfide () are a promising way to provide a sizeable amount of hysteresis at low energy costs. Herein, different configurations of memristors as well as the mechanisms involved in hysteresis formation are shown. Bottom gated configuration is beneficial in terms of hysteresis area and energy efficiency. The impact of device channel dimensions on the hysteresis area and energy consumption is discussed. Different operation conditions with triangular, rectangular, sinusoidal, and sawtooth drain‐to‐source pulses are simulated, and rectangular pulses demonstrate the highest energy efficiency. The study shows the potential to realize low‐power neuromorphic systems using memristive devices.

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Section: Resultsmentioning

confidence: 99%

Section: Device Dimensions and Simulation Parametersmentioning

confidence: 99%

“…Traps capture probability for both volume and surface traps was fitted using experimental data demonstrated in refs. [12,18].…”

Section: Device Dimensions and Simulation Parametersmentioning

confidence: 99%

\left(\text{MoS}\right)_{2}

volume.…”

Section: Device Description and Operation Conditionsmentioning

confidence: 99%

“…We present a comprehensive analysis of the electrical characteristics of

\left(\text{MoS}\right)_{2}

memristors based on simulations in terms of the intrinsic‐oxide traps model. [ 12 ] We discuss the influence of various factors, such as the thickness of the

\left(\text{MoS}\right)_{2}

layer, channel length and gate configuration (top or bottom gate), and the applied voltage pulse form on the

\left(\text{MoS}\right)_{2}

memristors hysteresis response. The energy efficiency of different memristor configurations is compared using the ratio of the hysteresis area to the consumed energy.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Energy‐Efficient Operation Conditions of MoS₂‐Based Memristors

Kurtash

Jacobs

Pezoldt

2023

Physica Status Solidi (a)

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Three-Dimensional MoS2 Nanosheet Structures: CVD Synthesis, Characterization, and Electrical Properties

et al. 2023

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The proposed study demonstrates a single-step CVD method for synthesizing three-dimensional vertical MoS2 nanosheets. The postulated synthesizing approach employs a temperature ramp with a continuous N2 gas flow during the deposition process. The distinctive signals of MoS2 were revealed via Raman spectroscopy study, and the substantial frequency difference in the characteristic signals supported the bulk nature of the synthesized material. Additionally, XRD measurements sustained the material’s crystallinity and its 2H-MoS2 nature. The FIB cross-sectional analysis provided information on the origin and evolution of the vertical MoS2 structures and their growth mechanisms. The strain energy produced by the compression between MoS2 islands is assumed to primarily drive the formation of vertical MoS2 nanosheets. In addition, vertical MoS2 structures that emerge from micro fissures (cracks) on individual MoS2 islands were observed and examined. For the evaluation of electrical properties, field-effect transistor structures were fabricated on the synthesized material employing standard semiconductor technology. The lateral back-gated field-effect transistors fabricated on the synthesized material showed an n-type behavior with field-effect mobility of 1.46 cm2 V−1 s−1 and an estimated carrier concentration of 4.5 × 1012 cm−2. Furthermore, the effects of a back-gate voltage bias and channel dimensions on the hysteresis effect of FET devices were investigated and quantified.

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Defects Contributing to Hysteresis in Few-Layer and Thin-Film MoS2 Memristive Devices

Abedin,

Kurtash,

Mathew

et al. 2024

Materials

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Molybdenum disulfide, a two-dimensional material extensively explored for potential applications in non-von Neumann computing technologies, has garnered significant attention owing to the observed hysteresis phenomena in MoS2 FETs. The dominant sources of hysteresis reported include charge trapping at the channel–dielectric interface and the adsorption/desorption of molecules. However, in MoS2 FETs with different channel thicknesses, the specific nature and density of defects contributing to hysteresis remain an intriguing aspect requiring further investigation. This study delves into memristive devices with back-gate modulated channel layers based on CVD-deposited flake-based and thin-film-based MoS2 FETs, with a few-layer (FL) and thin-film (TF) channel thickness. Analysis of current–voltage (I−V) and conductance–frequency (Gp/ω−f) measurements led to the conclusion that the elevated hysteresis observed in TF MoS2 devices, as opposed to FL devices, stems from a substantial contribution from intrinsic defects within the channel volume, surpassing that of interface defects. This study underscores the significance of considering both intrinsic defects within the bulk and the interface defects of the channel when analyzing hysteresis in MoS2 FETs, particularly in TF FETs. The selection between FL and TF MoS2 devices depends on the requirements for memristive applications, considering factors such as hysteresis tolerance and scaling capabilities.

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Hysteresis Associated with Intrinsic-Oxide Traps in Gate-Tunable Tetrahedral CVD-MoS2 Memristor

Cited by 3 publications

References 13 publications

Energy‐Efficient Operation Conditions of MoS₂‐Based Memristors

Energy‐Efficient Operation Conditions of MoS₂‐Based Memristors

Three-Dimensional MoS2 Nanosheet Structures: CVD Synthesis, Characterization, and Electrical Properties

Defects Contributing to Hysteresis in Few-Layer and Thin-Film MoS2 Memristive Devices

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Hysteresis Associated with Intrinsic-Oxide Traps in Gate-Tunable Tetrahedral CVD-MoS2 Memristor

Cited by 3 publications

References 13 publications

Energy‐Efficient Operation Conditions of MoS2‐Based Memristors

Energy‐Efficient Operation Conditions of MoS2‐Based Memristors

Three-Dimensional MoS2 Nanosheet Structures: CVD Synthesis, Characterization, and Electrical Properties

Defects Contributing to Hysteresis in Few-Layer and Thin-Film MoS2 Memristive Devices

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Product

Resources

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Energy‐Efficient Operation Conditions of MoS₂‐Based Memristors

Energy‐Efficient Operation Conditions of MoS₂‐Based Memristors