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Though the multilevel inverters hold attractive features, usage of more switches in the conventional configuration poses a limitation to its wide range application. Therefore, a renewed 7-level multilevel inverter topology is introduced incorporating the least number of unidirectional switches and gate trigger circuitry, thereby ensuring the minimum switching losses, reducing size and installation cost. The new topology is well suited for drives and renewable energy applications. The performance quality in terms of THD and switching losses of the new MLI is compared with conventional cascaded MLI and other existing 7-level reduced switch topologies using carrier-based PWM techniques. The results are validated using MATLAB/SIMULINK.

A multilevel inverter is a power electronic device that is used for high voltage and high power applications, with the added advantages of low switching stress and lower total harmonic distortion (THD), hence reducing the size and bulk of the passive filters. This paper proposes a new topology of a cascaded multilevel inverter that utilizes less number of switches than the conventional topology. Therefore with less number of switches in the circuit, there will be a reduction in the gate driver circuits and also in effect fewer switches will be conducting for specific intervals of time. The circuitry consists of smaller multilevel inverter blocks connected in series to achieve its characteristic output waveform. A seven level inverter will be simulated with the implementation of PWM techniques and its effect on the harmonic spectrum will be analyzed. The system will be modelled with the help of MATLAB/SIMULINK.

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