Back side exposure of variable size through silicon viasDual damascene dielectric etch technology is emerging as a key enabler for advanced integration schemes. Early implementations of copper dual damascene processes favored the trench-first approach. This approach has now been largely superseded by the via-first scheme for technology nodes below 250 nm. Several etch issues typically arise when implementing either of these approaches. The via-first approach can lead to either via veils or excessive faceting problems when the trench is etched. The traditional trench-first approach requires long via overetches and very high selectivity to the underlayer so that allowance can be made for vias that are misaligned or placed outside the trenches. Trench-first lithography employing organic resists often requires patterning over nonplanar surfaces, which can result in narrow process windows. Both the via-first and trench-first approaches increasingly require etching the trench without a stop layer. This places exacting demands on etch uniformity, etch front control, and sidewall profile angle control. Control of these issues is enhanced when the etch mechanisms responsible for driving them are understood. These and other issues as well as the current understanding of the relevant mechanisms are discussed for implementing copper dual damascene structures in plasma enhanced chemical vapor deposition undoped silicate glass or fluorinated silicate glass oxide films.
Today angular rate sensors (gyroscopes) for automotive application are fabricated by a silicon surface micromachining process (SMM). One critical performance parameter of these micromachined vibratory gyroscopes is the mechanical coupling between the drive and sense mode due to manufacturing imperfections. Excessive coupling, called quadrature error, leads to large zero rate output (ZRO or QBias). This paper discusses for the first time, the dependence between quadrature error and profile asymmetries in relevant spring structures with respect to non-uniformities of the silicon deep reactive ion etch (Si DRiE) systems used for the SMM processing.
The resulting temperature distribution of a silicon wafer held by an electrostatic chuck (ESC) in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor is characterized and modeled. The effects of the clamping voltage VESC, pressure between the ESC and wafer PHe, and the surface finish and pattern on the ESC are investigated. Heat transfer coefficients between the wafer and various ESCs are determined experimentally. A model is developed to predict the temperature distribution at the surface of the wafer, and used to explain the experimentally observed temperature variations both within wafer and between different chucks. The model is then used to aid in the design of an ESC which provides improved temperature uniformity at the wafer surface. The results of this study indicate: (a) the thermal resistances across the interface between the wafer and ESC control both the absolute wafer temperature and the wafer temperature uniformity; (b) the surface roughness of the ESC and the size of the ‘‘contact’’ regions are major design factors controlling the absolute temperature of the wafer—the temperature can be adjusted by varying the value of VESC and fine tuned by adjusting the value of PHe; (c) the nonuniform temperature distribution across the wafer surface is dictated by the surface pattern on the ESC, the variation in surface roughness, and the size of the ESC relative to the wafer; (d) wafer temperature variations from chuck to chuck are reduced by controlling the surface finish of the ESC and by ensuring that PHe is a dominant heat transfer mechanism; and (e) maximum uniformity in the temperature of the wafer is obtained when the radius of the ESC is matched as closely as possible to that of the wafer. We have shown that numerical heat transfer models can be used to optimize the geometry of the ESC to provide a uniform distribution of temperature across the surface of the wafer.
Gate oxide damage resulting from high density plasma chemical vapor deposition of silicon oxide was investigated using damage sensitive antenna structures with area ratios up to 200,000:1. Significant damage was detected from an unoptimized oxide deposition process. A 24-1 fractional factorial experimental design was used to screen the effect of four parameters: radio frequency power, microwave power, electrostatic chuck potential, and magnetic field. RF power and electrostatic chuck potential made no contribution to oxide degradation. The main factor was microwave power, and further experiments with microwave power ranging from 1500 to 2500 W showed that gate charging damage increased with microwave power, with the extent and distribution of damage depending on the magnetic field shape.
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