Customized voltage waveforms composed of a number of frequencies and used as the excitation of radio-frequency plasmas can control various plasma parameters such as energy distribution functions, homogeneity of the ionflux or ionization dynamics. So far this technology, while being extensively studied in academia, has yet to be established in applications. One reason for this is the lack of a suitable multi-frequency matching network that allows for maximum power absorption for each excitation frequency that is generated and transmitted via a single broadband amplifier.In this work, a method is introduced for designing such a network based on network theory and synthesis. Using this method, a circuit simulation is established that connects an exemplary matching network to an equivalent circuit plasma model of a capacitive radio-frequency discharge.It is found that for a range of gas pressures and number of excitation frequencies the matching conditions can be satisfied, which proves the functionality and feasibility of the proposed concept.Based on the proposed multi-frequency impedance matching, tailored voltage waveforms can be used at an industrial level.
Etch rate control in a 27 MHz reactive ion etching system for ultralarge scale integrated circuit processing Characterization of the etch rate non-uniformity in a magnetically enhanced reactive ion etcher Recent advances in ultralarge-scale integration have typically depended on reductions in etched feature size. This has motivated efforts to find etch processes that will precisely etch increasingly smaller features while retaining the ability to etch larger features. As feature sizes push below 0.25 m, reactive ion etch ͑RIE͒ lag control becomes increasingly important. Knowing how RIE lag scales with feature size for a given process aids in determining if that process must be discarded and a new one developed. In those situations where a process cannot be discarded, an understanding of RIE lag scaling aids in predicting fabrication difficulties for a given device design. Using a minimal set of initial assumptions, it is shown that a relationship can be derived which relates etch rate to the time development of the feature aspect ratio. It is then shown that this relationship can be used to derive an expression for the etch depth as a function of time and feature size. The assumptions made are justified by phenomenological observation rather than by an assumed mechanism. This approach enhances the generality of the results obtained, thus making them useful for a variety of practical etch engineering applications.
A capacitive discharge connected through a dielectric or metal slot to a peripheral grounded region is a configuration of both theoretical and practical interest . The configuration is used in commercial dual frequency capacitive discharges, where a dielectric slot surrounding the substrate separates the main plasma from the peripheral grounded pumping region. Ignition of the peripheral plasma produces effects such as poor matching and relaxation oscillations that are detrimental to processing performance. Discharge models are developed for diffusion and plasma maintenance in the slot, and plasma maintenance in the periphery. The theoretical predictions of ignition conditions as a function of voltage and pressure are compared with experimental results for a driving frequency of 27.12 MHz and a gap spacing of 0.635 cm connecting the two regions, giving good agreement.
Back side exposure of variable size through silicon viasDual damascene dielectric etch technology is emerging as a key enabler for advanced integration schemes. Early implementations of copper dual damascene processes favored the trench-first approach. This approach has now been largely superseded by the via-first scheme for technology nodes below 250 nm. Several etch issues typically arise when implementing either of these approaches. The via-first approach can lead to either via veils or excessive faceting problems when the trench is etched. The traditional trench-first approach requires long via overetches and very high selectivity to the underlayer so that allowance can be made for vias that are misaligned or placed outside the trenches. Trench-first lithography employing organic resists often requires patterning over nonplanar surfaces, which can result in narrow process windows. Both the via-first and trench-first approaches increasingly require etching the trench without a stop layer. This places exacting demands on etch uniformity, etch front control, and sidewall profile angle control. Control of these issues is enhanced when the etch mechanisms responsible for driving them are understood. These and other issues as well as the current understanding of the relevant mechanisms are discussed for implementing copper dual damascene structures in plasma enhanced chemical vapor deposition undoped silicate glass or fluorinated silicate glass oxide films.
A systematic study of trench profile evolution in a medium-density oxide etch reactor is presented. A Langmuir site balance model is developed in the limit of unity sticking coefficient which exhibits a flat etch front as is frequently required for dual damascene applications. The model indicates that it is desirable to operate in a neutral-limited ion-assisted etch regime. Physical sputtering is also shown to be necessary, but this etch contribution must be kept small with respect to the ion-assisted etch rate. The model also indicates how either microtrenching or bottom rounding may be controlled or avoided altogether. Model predictions are compared with experimental data obtained from a Lam Research 4520XLE medium density reactor. This work includes a study of the trench bottom rounding dependencies upon pressure, etch time, aspect ratio, and process gas flow for a fluorocarbon-based etch process. The model is shown to qualitatively capture experimentally observed process trends. In some regimes, good quantitative agreement with observed measurement is seen. It can thus serve as a useful guide for trench etch process development.
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