We describe a quantitative relationship between ID and V, driven NBTl specifications. Mobility degradation is shown to be a significant (-40%) contributor to ID degradation. We report for the first time, degradation in gate-drain capacitance (CGo) due to NBTI. The impact of this COD degradation on circuit performance is quantified for both digital and analog circuits. We find that CGD degradation has a greater impact on the analog circuit studied than the digital circuit. We demonstrate that there is an optimum operating voltage that balances NBTI degradation against transistor voltage headroom. Further, a numerical model based on the reaction-diffision theory has been developed, which is found to satisfactorily describe degradation, recovery and postrecovery response to stress.
The dc characteristics of Si1−x−yGexCy P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) were evaluated between room temperature and 77 K and were compared to those of Si and Si1−xGex PMOSFETs. The low-field effective mobility in Si1−x−yGexCy devices is found to be higher than that of Si1−xGex (grown in the metastable regime) and Si devices at low gate bias and room temperature. However, with increasing transverse fields and with decreasing temperatures, Si1−x−yGexCy devices show degraded performance. The enhancement at low gate bias is attributed to the strain stabilization effect of C. This application of Si1−x−yGexCy in PMOSFETs demonstrates potential benefits in the use of C for strain stabilization of the binary alloy.
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