A discrete-time Bluetooth receiver in a 0.13μm digital CMOS process

A low-power highly digitized receiver for 2.4-GHz-band GFSK applications

“…The supply voltage for the analog part is 1.8 V, whereas the digital supply voltage is 1.4 V. The total power consumption is 31.7 mW in continuous mode. This is at least a factor of two lower than for other reported CMOS receivers with identical functionality [1]- [5].…”

“…Several transceivers realized in CMOS and aimed at Bluetooth/Gaussian frequency-shift keying (GFSK) applications have been reported in the literature [1]- [5]. Most referenced transceivers have been realized in 0.18-m CMOS, whereas the Bluetooth receiver revealed in [5] has been realized in 0.13-m CMOS.…”

“…Most referenced transceivers have been realized in 0.18-m CMOS, whereas the Bluetooth receiver revealed in [5] has been realized in 0.13-m CMOS. All cited references report power consumptions for the receiver part of over 60 mW.…”

“…This enables digital demodulation, but this has not been included in the presented silicon. The receiver architecture presented in [5] is also linear and performs demodulation in the digital domain. Discrete-time analog signal processing is applied at the input involving RF sampling with an all-digital phase-locked loop (PLL) using a digitally controlled oscillator.…”

On the Suitability of Discrete-Time Receivers for Software-Defined Radio

“…Recently, the feasibility of CMOS D-T radio receivers using RF sampling has been demonstrated for Bluetooth [1], GSM/GPRS [2] and WLAN [3]. As shown in Fig.…”