Soft error mitigation schemes inherently lead to penalties in terms of area usage, power consumption and/or performance metrics. This work provides a radiation hardening efficiency analysis of two possible selective node hardening based on standard cells: Gate Sizing and Transistor Stacking. The impact on the Single-Event Transient cross-section, layout area and leakage current is discussed. The results indicate that both techniques provide the same area overhead and high efficiency for low particle linear energy transfer. Further, although transistor stacking exhibits lower static power consumption, gate sizing still presents the best trade-off between area, performance and reliability.
Single-Event Latchup (SEL) concerns CMOS technology as a major reliability issue and it is influenced by different parameters. In this work, the effect of the temperature variation on SELhas been investigated and its effect has been analyzed combining the variation of three parameters related to the geometry and to the design of the component: doping profile, anode to cathode spacing (A-C spacing) and substrate and well taps placement. 2D TCAD simulations have been performed, using an NPNP structure based on 65nm CMOS inverter. From these simulations, we have analyzed threshold LET and SEL rate. Results show that temperature impact is stronger when the component is less sensitive to SEL.
Single-Event Latchup (SEL) is considered as a major reliability issue for the CMOS technology due to its capability of permanently damaging electronic components. In this work, the impact of temperature variation on the SEL mechanism is investigated. As the SEL sensitivity is influenced by design and environment parameters, the temperature variation is also evaluated along the variation of three parameters related to the geometry and to the design of the component: the doping profile, the anode to cathode spacing (A-C spacing) and the substrate and well taps placement. Moreover, the charge collection process has been analyzed. The goal was to verify whether the concept of critical charge, through studying the collected charge by the source implants, can be used for SEL, as it is used for upsets. 2D TCAD simulations have been performed, using an NPNP structure based on 65nm CMOS inverter. From these simulations, we have analyzed the threshold LET and SEL rate. Results show that temperature impact is stronger when the component is less sensitive to SEL. Moreover, charge collected has shown promising results about its usage for SEL.
In this paper SEL cross sections were calculated from TCAD simulations varying doping profiles and anode-to-cathode spacing values. We found that doping profiles variation has a stronger impact on SEL sensitivity then variation of spacing.
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