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The InP-based pseudomorphic high electron mobility transistor (p-HEMT) is an attractive device technology for future high-speed and low-power digital integrated circuit applications beyond THz bandwidth. To date, though, most of researches for high-speed applications have been focused on depletion-mode HEMTs (D-HEMTs) since enhancement-mode (E-mode) HEMTs suffer from high access resistances associated with a low carrier concentration in the channel [1]. Clearly, E-mode FETs play an important role for applications including a single power supply and a direct-coupled FET logic [2][3][4]. In order to fabricate E-mode HEMTs without an excessive access resistance a recessed gate structure implemented by wet or dry etching of the barrier layer and a buried Pt gate technology was used. Recently, we have successfully demonstrated a low damage Ne-based atomic layer etching (ALET) technology to selectively etch an InP etch stopper in a two-step gate recess process [5]. In this work, we present characteristics of 130 nm E-mode InAs p-HEMTs implemented by combination of the ALET technology and the buried Pt technology for improved device performance.The device showed f T and f max greater than 400 GHz. To our knowledge, this is the best combination of f T and f max for any E-mode HEMTs having the gate length of 130 nm. Fig. 1 shows the epitaxial layer structure of the InAs p-HEMTs. A 6 nm InAs sub-channel was used for improved carrier transport in the channel [6]. Measured 2-DEG sheet carrier density and Hall mobility were 3.2×10 12 cm -2 and 13,000 cm 2 /V·sec at 300 K. Device fabrication began with a mesa isolation down to the InAlAs buffer layer by a wet chemical etching. After source and drain ohmic metallization (Ni/Ge/Au = 100/450/1500 Å) subsequent rapid thermal annealing at 275 ºC under N 2 ambient was performed. Then, pad patterns for ground-signal-ground probing were defined by lift-off of Ti/Au metallization. After coating tri-layer e-beam resists (ZEP520A/PMGI/ZEP520A), a double e-beam exposure method was used to define a 130 nm T-gate. After the n-InGaAs/n-InAlAs multi-layer cap was isotropically removed by a citric acid-based selective wet solution, the low damage Ne-based ALET technology was applied to anisotropically remove the remaining InP etch-stop layer. The ALET technology, which used a low plasma energy to remove monolayer of InP per unit etch-cycle (corresponding to the InP etch rate of 1.47 Å/cycle), had an extremely high etch selectivity of 70 against the underlying InAlAs barrier layer. It also exhibited smooth In 0.52 Al 0.48 As surface and insignificant change of stoichiometry [5]. After Pt/Ti/Pt/Au (30/200/200/3000 Å) Schottky gate was evaporated and lifted off, the samples were finally annealed at 250 °C under N 2 environment to form the buried Pt gate. Fig. 2 shows a cross-sectional STEM image of the fabricated 130 nm InAs p-HEMTs having the buried Pt gate. The thickness of the InAlAs barrier layer measured by EDX analysis was around 5 nm. Fig. 3 and Fig. 4 show the typical I DS -V DS character...

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