The wireless communication in the next generation is bound to be driven by massive machine-type communication or in other words Internet-of-things (IoT). In the near future, the need for effective communication and higher data processing rates will require IoT devices to support 5G networks. For 5G IoT applications in the ultra-wideband range (3.1-10.6 GHz), the analog receivers must provide both high-performance and energy efficiency simultaneously. This work addresses the demands of 5G IoT analog receivers by proposing an ultra-low-power low noise amplifier (LNA) employing cross-coupled positive shunt feedback. The proposed LNA is designed in UMC 180 nm deep n-well process, and the post-layout characterization is done using Cadence SpectreRF. The proposed design achieves a peak gain of 9.94 dB and a noise figure of 3.2-1.086 dB along the usable bandwidth of 3.2-9.625 GHz while consuming an ultra-low-power of 493 µW from a 1-V power supply. The maximum input-referred third-order intercept point of 8.81 dBm is attained for an input signal at 2.4 GHz and the interferer as close as 2.425 GHz. The LNA consumes a minimal layout area of only 676.2 µm × 350.7 µm. The proposed LNA has the better figure-of-merit while consuming almost 50% less power than the recently reported sub-mW LNA in literature.
The emerging 5G internet-of-things applications in home automation, smart wearables, healthcare monitoring, automotive sensors require low-cost, area efficient, high-performance and low power radio frequency blocks for effective short-range communication. This growing market demand is addressed in this paper by proposing a fully CMOS RF down-converter (RFDC) network for 5G applications. This work aims to achieve high linearity, low noise figure and high gain simultaneously by optimally splitting the performance between the three stages of the RFDC. The proposed downconversion system is designed in UMC 180 nm CMOS process technology and the post-layout simulations on layout extracted parameters with Cadence SpectreRF shows an IIP3 of − 3.43 dBm, an IIP2 of 78.13 dBm, double-sideband noise figure of 12.76 dB, a conversion gain of 23.69 dB, the spurious-free dynamic range of 71.7 dB, and the phase noise of − 91.39 dBc/Hz at an offset of 5 MHz. The proposed frequency translation circuit occupies a core area of only 0.0043 mm 2 and consumes a low power of 12.6 mW from a 1.8 V supply.
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