The wireless communication in the next generation is bound to be driven by massive machine-type communication or in other words Internet-of-things (IoT). In the near future, the need for effective communication and higher data processing rates will require IoT devices to support 5G networks. For 5G IoT applications in the ultra-wideband range (3.1-10.6 GHz), the analog receivers must provide both high-performance and energy efficiency simultaneously. This work addresses the demands of 5G IoT analog receivers by proposing an ultra-low-power low noise amplifier (LNA) employing cross-coupled positive shunt feedback. The proposed LNA is designed in UMC 180 nm deep n-well process, and the post-layout characterization is done using Cadence SpectreRF. The proposed design achieves a peak gain of 9.94 dB and a noise figure of 3.2-1.086 dB along the usable bandwidth of 3.2-9.625 GHz while consuming an ultra-low-power of 493 µW from a 1-V power supply. The maximum input-referred third-order intercept point of 8.81 dBm is attained for an input signal at 2.4 GHz and the interferer as close as 2.425 GHz. The LNA consumes a minimal layout area of only 676.2 µm × 350.7 µm. The proposed LNA has the better figure-of-merit while consuming almost 50% less power than the recently reported sub-mW LNA in literature.
Due to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.
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