Ovonic Phase-Change Materials have found a renewed interest in the recent times owing to their applications in Non-Volatile Random Access Memories. In the present work, a cost-effective high voltage electrical switching analyzer has been developed to enable investigations on the I-V characteristics and electrical switching of bulk solids, which are necessary for identifying suitable materials for memory and other applications such as power control. The developed set up mainly consists of a PC based programmable High Voltage DC Power Supply which acts as an excitation source and a high speed Digital Storage Oscilloscope. For flexible control options, a Graphical User Interface has also been developed using LabVIEW-6i to control the excitation source through the analog outputs of a data acquisition card. Options are made in the system to sweep the output voltage from 45 to 1750 V or the output current in the range 0-45 mA with resolutions of 1.5 V & 5 or 50 µA at variable rates. I-V characteristics and switching behavior of the sample material are instantaneously acquired on the storage oscilloscope and transferred to PC for post processing. The system can be used to investigate a broad range of materials and some typical results are presented to illustrate the capability of the system developed. The closed-loop stability of the system has also been confirmed by frequency response plots.
Body coupled communication (BCC) is an efficient networking approach to body area network (BAN) based on Human-centric communication. The BCC provides interference only between humans in very close proximity. In this work, an efficient Physical layer (PHY) based digital transceiver) is designed for BCC. The digital transceiver Module mainly contains a Digital transmitter (TX) with Manchester encoder, clock synchronization unit, and Digital receiver (RX) with Manchester decoder. The TX and RX modules are designed using a finite state machine as per the IEEE 802.3 Standards. The complete work is also varied for BAN applications by connecting two Application layer transceivers and two Physical layer-based digital transceivers. The architecture is simulated in a Model-sim simulator. The complete Module is synthesized using different FPGA families, and the hardware design constraints are contrasted. The digital transceiver works at 231.28 MHz operating frequency, consumes 0.113W power, and provides a 7.7 Mbps data rate and 4.67 Kbps/Slice efficiency on Artix-7 FPGA. The proposed transceiver is also compared with existing digital transceivers with hardware constraints improvements.
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